diff --git a/src/arch/x86/isa/operands.isa b/src/arch/x86/isa/operands.isa
index 2cd92ddb69..64c83c65cc 100644
--- a/src/arch/x86/isa/operands.isa
+++ b/src/arch/x86/isa/operands.isa
@@ -64,7 +64,7 @@ let {{
     def floatReg(idx, id):
         return ('FloatReg', 'df', idx, 'IsFloating', id)
     def ccReg(idx, id):
-        return ('CCReg', 'uqw', idx, 'IsCC', id)
+        return ('CCReg', 'uqw', idx, None, id)
     def controlReg(idx, id, ctype = 'uqw'):
         return ('ControlReg', ctype, idx,
                 (None, None, ['IsSerializeAfter',
@@ -147,20 +147,20 @@ def operands {{
         # would be retained, the write predicate checks if any of the bits
         # are being written.
 
-        'PredccFlagBits': ('CCReg', 'uqw', '(CCREG_ZAPS)', 'IsCC',
+        'PredccFlagBits': ('CCReg', 'uqw', '(CCREG_ZAPS)', None,
                 60, None, None, '''(((ext & (PFBit | AFBit | ZFBit | SFBit
                 )) != (PFBit | AFBit | ZFBit | SFBit )) &&
                 ((ext & (PFBit | AFBit | ZFBit | SFBit )) != 0))''',
                 '((ext & (PFBit | AFBit | ZFBit | SFBit )) != 0)'),
-        'PredcfofBits':   ('CCReg', 'uqw', '(CCREG_CFOF)', 'IsCC',
+        'PredcfofBits':   ('CCReg', 'uqw', '(CCREG_CFOF)', None,
                 61, None, None, '''(((ext & CFBit) == 0 ||
                 (ext & OFBit) == 0) && ((ext & (CFBit | OFBit)) != 0))''',
                 '((ext & (CFBit | OFBit)) != 0)'),
-        'PreddfBit':   ('CCReg', 'uqw', '(CCREG_DF)', 'IsCC',
+        'PreddfBit':   ('CCReg', 'uqw', '(CCREG_DF)', None,
                 62, None, None, '(false)', '((ext & DFBit) != 0)'),
-        'PredecfBit':   ('CCReg', 'uqw', '(CCREG_ECF)', 'IsCC',
+        'PredecfBit':   ('CCReg', 'uqw', '(CCREG_ECF)', None,
                 63, None, None, '(false)', '((ext & ECFBit) != 0)'),
-        'PredezfBit':   ('CCReg', 'uqw', '(CCREG_EZF)', 'IsCC',
+        'PredezfBit':   ('CCReg', 'uqw', '(CCREG_EZF)', None,
                 64, None, None, '(false)', '((ext & EZFBit) != 0)'),
 
         # These register should needs to be more protected so that later
diff --git a/src/cpu/StaticInstFlags.py b/src/cpu/StaticInstFlags.py
index 27ba013ed4..316aef4fab 100644
--- a/src/cpu/StaticInstFlags.py
+++ b/src/cpu/StaticInstFlags.py
@@ -56,7 +56,6 @@ class StaticInstFlags(Enum):
 
         'IsInteger',        # References integer regs.
         'IsFloating',       # References FP regs.
-        'IsCC',             # References CC regs.
         'IsVector',         # References Vector regs.
         'IsVectorElem',     # References Vector reg elems.
 
diff --git a/src/cpu/static_inst.hh b/src/cpu/static_inst.hh
index 353c0e3584..0a871cfc62 100644
--- a/src/cpu/static_inst.hh
+++ b/src/cpu/static_inst.hh
@@ -170,7 +170,6 @@ class StaticInst : public RefCounted, public StaticInstFlags
     bool isInteger()      const { return flags[IsInteger]; }
     bool isFloating()     const { return flags[IsFloating]; }
     bool isVector()       const { return flags[IsVector]; }
-    bool isCC()           const { return flags[IsCC]; }
 
     bool isControl()      const { return flags[IsControl]; }
     bool isCall()         const { return flags[IsCall]; }