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fastmodel: export CortexR52 reset and halt signals

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Change-Id: I44a26bad1a91009dbef586ab5d8eeee60352d51e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49651
Reviewed-by: Earl Ou <shunhsingou@google.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Yu-hsin Wang
2021-08-30 17:26:39 +08:00
parent f771ed96d7
commit 41093df363
8 changed files with 69 additions and 5 deletions
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8
src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py
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@@ -30,7 +30,7 @@ from m5.SimObject import SimObject
from m5.objects.ArmInterrupts import ArmInterrupts
from m5.objects.ArmISA import ArmISA
from m5.objects.FastModel import AmbaInitiatorSocket, AmbaTargetSocket
from m5.objects.IntPin import VectorIntSinkPin
from m5.objects.IntPin import IntSinkPin, VectorIntSinkPin
from m5.objects.Iris import IrisBaseCPU
from m5.objects.SystemC import SystemC_ScModule
@@ -46,6 +46,11 @@ class FastModelCortexR52(IrisBaseCPU):
llpp = AmbaInitiatorSocket(64, 'Low Latency Peripheral Port')
flash = AmbaInitiatorSocket(64, 'Flash')
amba = AmbaInitiatorSocket(64, 'AMBA initiator socket')
core_reset = IntSinkPin('Raising this signal will put the core into ' \
'reset mode.')
poweron_reset = IntSinkPin('Power on reset. Initializes all the ' \
'processor logic, including debug logic.')
halt = IntSinkPin('Raising this signal will put the core into halt mode.')
CFGEND = Param.Bool(False, "Endianness configuration at reset. 0, " \
"little endian. 1, big endian.")
@@ -108,6 +113,7 @@ class FastModelCortexR52Cluster(SimObject):
spi = VectorIntSinkPin('SPI inputs (0-959)')
ext_slave = AmbaTargetSocket(64, 'AMBA target socket')
top_reset = IntSinkPin('This signal resets timer and interrupt controller.')
CLUSTER_ID = Param.UInt16(0, "CLUSTER_ID[15:8] equivalent to " \
"CFGMPIDRAFF2, CLUSTER_ID[7:0] equivalent to CFGMPIDRAFF1")

6
src/arch/arm/fastmodel/CortexR52/cortex_r52.cc
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@@ -86,7 +86,9 @@ CortexR52::getPort(const std::string &if_name, PortID idx)
// Since PPIs are indexed both by core and by number, modify the name
// to hold the core number.
return evs->gem5_getPort(csprintf("%s_%d", if_name, num), idx);
} else if (if_name == "amba" || if_name == "llpp" || if_name == "flash") {
} else if (if_name == "amba" || if_name == "llpp" || if_name == "flash" ||
if_name == "core_reset" || if_name == "poweron_reset" ||
if_name == "halt") {
// Since these ports are scalar per core, use the core number as the
// index. Also verify that that index is not being used.
assert(idx == InvalidPortID);
@@ -150,7 +152,7 @@ CortexR52Cluster::getPort(const std::string &if_name, PortID idx)
{
if (if_name == "spi") {
return evs->gem5_getPort(if_name, idx);
} else if (if_name == "ext_slave") {
} else if (if_name == "ext_slave" || if_name == "top_reset") {
assert(idx == InvalidPortID);
return evs->gem5_getPort(if_name, idx);
} else {

21
src/arch/arm/fastmodel/CortexR52/evs.cc
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@@ -68,12 +68,18 @@ ScxEvsCortexR52<Types>::CorePins::CorePins(Evs *_evs, int _cpu) :
evs(_evs), cpu(_cpu),
llpp(evs->llpp[cpu], name + ".llpp", -1),
flash(evs->flash[cpu], name + ".flash", -1),
amba(evs->amba[cpu], name + ".amba", -1)
amba(evs->amba[cpu], name + ".amba", -1),
core_reset(name + ".core_reset", 0),
poweron_reset(name + ".poweron_reset", 0),
halt(name + ".halt", 0)
{
for (int i = 0; i < Evs::PpiCount; i++) {
ppis.emplace_back(
new CoreInt(csprintf("%s.ppi[%d]", name, i), i, this));
}
core_reset.signal_out.bind(evs->core_reset[cpu]);
poweron_reset.signal_out.bind(evs->poweron_reset[cpu]);
halt.signal_out.bind(evs->halt[cpu]);
}
@@ -82,7 +88,8 @@ ScxEvsCortexR52<Types>::ScxEvsCortexR52(
const sc_core::sc_module_name &mod_name, const Params &p) :
Base(mod_name),
params(p),
ext_slave(Base::ext_slave, p.name + ".ext_slave", -1)
ext_slave(Base::ext_slave, p.name + ".ext_slave", -1),
top_reset(p.name + ".top_reset", 0)
{
for (int i = 0; i < CoreCount; i++)
corePins.emplace_back(new CorePins(this, i));
@@ -92,6 +99,8 @@ ScxEvsCortexR52<Types>::ScxEvsCortexR52(
new ClstrInt(csprintf("%s.spi[%d]", name(), i), i, this));
}
top_reset.signal_out.bind(Base::top_reset);
clockRateControl.bind(this->clock_rate_s);
signalInterrupt.bind(this->signal_interrupt);
}
@@ -116,8 +125,16 @@ ScxEvsCortexR52<Types>::gem5_getPort(const std::string &if_name, int idx)
return this->corePins.at(idx)->flash;
} else if (if_name == "amba") {
return this->corePins.at(idx)->amba;
} else if (if_name == "core_reset") {
return this->corePins.at(idx)->core_reset;
} else if (if_name == "poweron_reset") {
return this->corePins.at(idx)->poweron_reset;
} else if (if_name == "halt") {
return this->corePins.at(idx)->halt;
} else if (if_name == "ext_slave") {
return this->ext_slave;
} else if (if_name == "top_reset") {
return this->top_reset;
} else if (if_name == "spi") {
return *this->spis.at(idx);
} else if (if_name.substr(0, 3) == "ppi") {

7
src/arch/arm/fastmodel/CortexR52/evs.hh
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@@ -32,6 +32,7 @@
#include "arch/arm/fastmodel/amba_ports.hh"
#include "arch/arm/fastmodel/common/signal_receiver.hh"
#include "arch/arm/fastmodel/common/signal_sender.hh"
#include "arch/arm/fastmodel/iris/cpu.hh"
#include "arch/arm/fastmodel/protocol/exported_clock_rate_control.hh"
#include "arch/arm/fastmodel/protocol/signal_interrupt.hh"
@@ -102,6 +103,10 @@ class ScxEvsCortexR52 : public Types::Base, public Iris::BaseCpuEvs
AmbaInitiator llpp;
AmbaInitiator flash;
AmbaInitiator amba;
SignalSender core_reset;
SignalSender poweron_reset;
SignalSender halt;
};
std::vector<std::unique_ptr<CorePins>> corePins;
@@ -116,6 +121,8 @@ class ScxEvsCortexR52 : public Types::Base, public Iris::BaseCpuEvs
AmbaTarget ext_slave;
SignalSender top_reset;
public:
ScxEvsCortexR52(const Params &p) : ScxEvsCortexR52(p.name.c_str(), p) {}
ScxEvsCortexR52(const sc_core::sc_module_name &mod_name, const Params &p);

8
src/arch/arm/fastmodel/CortexR52/x1/x1.lisa
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@@ -45,6 +45,10 @@ component CortexR52x1
core.flash_m => self.flash;
core.pvbus_core_m => self.amba;
self.ext_slave => core.ext_slave_s;
self.core_reset => core.reset;
self.poweron_reset => core.cpuporeset;
self.top_reset => core.topreset;
self.halt => core.cpuhalt;
// Clocks.
clock1Hz.clk_out => clockDiv.clk_in;
@@ -66,6 +70,10 @@ component CortexR52x1
master port<PVBus> flash[1];
master port<PVBus> amba[1];
slave port<PVBus> ext_slave;
slave port<Signal> core_reset[1];
slave port<Signal> poweron_reset[1];
slave port<Signal> halt[1];
slave port<Signal> top_reset;
slave port<ExportedClockRateControl> clock_rate_s
{

8
src/arch/arm/fastmodel/CortexR52/x2/x2.lisa
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@@ -45,6 +45,10 @@ component CortexR52x2
core.flash_m => self.flash;
core.pvbus_core_m => self.amba;
self.ext_slave => core.ext_slave_s;
self.core_reset => core.reset;
self.poweron_reset => core.cpuporeset;
self.top_reset => core.topreset;
self.halt => core.cpuhalt;
// Clocks.
clock1Hz.clk_out => clockDiv.clk_in;
@@ -67,6 +71,10 @@ component CortexR52x2
master port<PVBus> flash[2];
master port<PVBus> amba[2];
slave port<PVBus> ext_slave;
slave port<Signal> core_reset[2];
slave port<Signal> poweron_reset[2];
slave port<Signal> halt[2];
slave port<Signal> top_reset;
slave port<ExportedClockRateControl> clock_rate_s
{

8
src/arch/arm/fastmodel/CortexR52/x3/x3.lisa
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@@ -45,6 +45,10 @@ component CortexR52x3
core.flash_m => self.flash;
core.pvbus_core_m => self.amba;
self.ext_slave => core.ext_slave_s;
self.core_reset => core.reset;
self.poweron_reset => core.cpuporeset;
self.top_reset => core.topreset;
self.halt => core.cpuhalt;
// Clocks.
clock1Hz.clk_out => clockDiv.clk_in;
@@ -68,6 +72,10 @@ component CortexR52x3
master port<PVBus> flash[3];
master port<PVBus> amba[3];
slave port<PVBus> ext_slave;
slave port<Signal> core_reset[3];
slave port<Signal> poweron_reset[3];
slave port<Signal> halt[3];
slave port<Signal> top_reset;
slave port<ExportedClockRateControl> clock_rate_s
{

8
src/arch/arm/fastmodel/CortexR52/x4/x4.lisa
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@@ -45,6 +45,10 @@ component CortexR52x4
core.flash_m => self.flash;
core.pvbus_core_m => self.amba;
self.ext_slave => core.ext_slave_s;
self.core_reset => core.reset;
self.poweron_reset => core.cpuporeset;
self.top_reset => core.topreset;
self.halt => core.cpuhalt;
// Clocks.
clock1Hz.clk_out => clockDiv.clk_in;
@@ -69,6 +73,10 @@ component CortexR52x4
master port<PVBus> flash[4];
master port<PVBus> amba[4];
slave port<PVBus> ext_slave;
slave port<Signal> core_reset[4];
slave port<Signal> poweron_reset[4];
slave port<Signal> halt[4];
slave port<Signal> top_reset;
slave port<ExportedClockRateControl> clock_rate_s
{