diff --git a/src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py b/src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py index 6530854242..710584df86 100644 --- a/src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py +++ b/src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py @@ -30,7 +30,7 @@ from m5.SimObject import SimObject from m5.objects.ArmInterrupts import ArmInterrupts from m5.objects.ArmISA import ArmISA from m5.objects.FastModel import AmbaInitiatorSocket, AmbaTargetSocket -from m5.objects.IntPin import VectorIntSinkPin +from m5.objects.IntPin import IntSinkPin, VectorIntSinkPin from m5.objects.Iris import IrisBaseCPU from m5.objects.SystemC import SystemC_ScModule @@ -46,6 +46,11 @@ class FastModelCortexR52(IrisBaseCPU): llpp = AmbaInitiatorSocket(64, 'Low Latency Peripheral Port') flash = AmbaInitiatorSocket(64, 'Flash') amba = AmbaInitiatorSocket(64, 'AMBA initiator socket') + core_reset = IntSinkPin('Raising this signal will put the core into ' \ + 'reset mode.') + poweron_reset = IntSinkPin('Power on reset. Initializes all the ' \ + 'processor logic, including debug logic.') + halt = IntSinkPin('Raising this signal will put the core into halt mode.') CFGEND = Param.Bool(False, "Endianness configuration at reset. 0, " \ "little endian. 1, big endian.") @@ -108,6 +113,7 @@ class FastModelCortexR52Cluster(SimObject): spi = VectorIntSinkPin('SPI inputs (0-959)') ext_slave = AmbaTargetSocket(64, 'AMBA target socket') + top_reset = IntSinkPin('This signal resets timer and interrupt controller.') CLUSTER_ID = Param.UInt16(0, "CLUSTER_ID[15:8] equivalent to " \ "CFGMPIDRAFF2, CLUSTER_ID[7:0] equivalent to CFGMPIDRAFF1") diff --git a/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc b/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc index 35e4e079d6..f5817f9ab8 100644 --- a/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc +++ b/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc @@ -86,7 +86,9 @@ CortexR52::getPort(const std::string &if_name, PortID idx) // Since PPIs are indexed both by core and by number, modify the name // to hold the core number. return evs->gem5_getPort(csprintf("%s_%d", if_name, num), idx); - } else if (if_name == "amba" || if_name == "llpp" || if_name == "flash") { + } else if (if_name == "amba" || if_name == "llpp" || if_name == "flash" || + if_name == "core_reset" || if_name == "poweron_reset" || + if_name == "halt") { // Since these ports are scalar per core, use the core number as the // index. Also verify that that index is not being used. assert(idx == InvalidPortID); @@ -150,7 +152,7 @@ CortexR52Cluster::getPort(const std::string &if_name, PortID idx) { if (if_name == "spi") { return evs->gem5_getPort(if_name, idx); - } else if (if_name == "ext_slave") { + } else if (if_name == "ext_slave" || if_name == "top_reset") { assert(idx == InvalidPortID); return evs->gem5_getPort(if_name, idx); } else { diff --git a/src/arch/arm/fastmodel/CortexR52/evs.cc b/src/arch/arm/fastmodel/CortexR52/evs.cc index f4e091ebbe..7f992f2459 100644 --- a/src/arch/arm/fastmodel/CortexR52/evs.cc +++ b/src/arch/arm/fastmodel/CortexR52/evs.cc @@ -68,12 +68,18 @@ ScxEvsCortexR52::CorePins::CorePins(Evs *_evs, int _cpu) : evs(_evs), cpu(_cpu), llpp(evs->llpp[cpu], name + ".llpp", -1), flash(evs->flash[cpu], name + ".flash", -1), - amba(evs->amba[cpu], name + ".amba", -1) + amba(evs->amba[cpu], name + ".amba", -1), + core_reset(name + ".core_reset", 0), + poweron_reset(name + ".poweron_reset", 0), + halt(name + ".halt", 0) { for (int i = 0; i < Evs::PpiCount; i++) { ppis.emplace_back( new CoreInt(csprintf("%s.ppi[%d]", name, i), i, this)); } + core_reset.signal_out.bind(evs->core_reset[cpu]); + poweron_reset.signal_out.bind(evs->poweron_reset[cpu]); + halt.signal_out.bind(evs->halt[cpu]); } @@ -82,7 +88,8 @@ ScxEvsCortexR52::ScxEvsCortexR52( const sc_core::sc_module_name &mod_name, const Params &p) : Base(mod_name), params(p), - ext_slave(Base::ext_slave, p.name + ".ext_slave", -1) + ext_slave(Base::ext_slave, p.name + ".ext_slave", -1), + top_reset(p.name + ".top_reset", 0) { for (int i = 0; i < CoreCount; i++) corePins.emplace_back(new CorePins(this, i)); @@ -92,6 +99,8 @@ ScxEvsCortexR52::ScxEvsCortexR52( new ClstrInt(csprintf("%s.spi[%d]", name(), i), i, this)); } + top_reset.signal_out.bind(Base::top_reset); + clockRateControl.bind(this->clock_rate_s); signalInterrupt.bind(this->signal_interrupt); } @@ -116,8 +125,16 @@ ScxEvsCortexR52::gem5_getPort(const std::string &if_name, int idx) return this->corePins.at(idx)->flash; } else if (if_name == "amba") { return this->corePins.at(idx)->amba; + } else if (if_name == "core_reset") { + return this->corePins.at(idx)->core_reset; + } else if (if_name == "poweron_reset") { + return this->corePins.at(idx)->poweron_reset; + } else if (if_name == "halt") { + return this->corePins.at(idx)->halt; } else if (if_name == "ext_slave") { return this->ext_slave; + } else if (if_name == "top_reset") { + return this->top_reset; } else if (if_name == "spi") { return *this->spis.at(idx); } else if (if_name.substr(0, 3) == "ppi") { diff --git a/src/arch/arm/fastmodel/CortexR52/evs.hh b/src/arch/arm/fastmodel/CortexR52/evs.hh index d0c1253b37..20870dfcfb 100644 --- a/src/arch/arm/fastmodel/CortexR52/evs.hh +++ b/src/arch/arm/fastmodel/CortexR52/evs.hh @@ -32,6 +32,7 @@ #include "arch/arm/fastmodel/amba_ports.hh" #include "arch/arm/fastmodel/common/signal_receiver.hh" +#include "arch/arm/fastmodel/common/signal_sender.hh" #include "arch/arm/fastmodel/iris/cpu.hh" #include "arch/arm/fastmodel/protocol/exported_clock_rate_control.hh" #include "arch/arm/fastmodel/protocol/signal_interrupt.hh" @@ -102,6 +103,10 @@ class ScxEvsCortexR52 : public Types::Base, public Iris::BaseCpuEvs AmbaInitiator llpp; AmbaInitiator flash; AmbaInitiator amba; + + SignalSender core_reset; + SignalSender poweron_reset; + SignalSender halt; }; std::vector> corePins; @@ -116,6 +121,8 @@ class ScxEvsCortexR52 : public Types::Base, public Iris::BaseCpuEvs AmbaTarget ext_slave; + SignalSender top_reset; + public: ScxEvsCortexR52(const Params &p) : ScxEvsCortexR52(p.name.c_str(), p) {} ScxEvsCortexR52(const sc_core::sc_module_name &mod_name, const Params &p); diff --git a/src/arch/arm/fastmodel/CortexR52/x1/x1.lisa b/src/arch/arm/fastmodel/CortexR52/x1/x1.lisa index 720d66f3f7..a15fe74b0f 100644 --- a/src/arch/arm/fastmodel/CortexR52/x1/x1.lisa +++ b/src/arch/arm/fastmodel/CortexR52/x1/x1.lisa @@ -45,6 +45,10 @@ component CortexR52x1 core.flash_m => self.flash; core.pvbus_core_m => self.amba; self.ext_slave => core.ext_slave_s; + self.core_reset => core.reset; + self.poweron_reset => core.cpuporeset; + self.top_reset => core.topreset; + self.halt => core.cpuhalt; // Clocks. clock1Hz.clk_out => clockDiv.clk_in; @@ -66,6 +70,10 @@ component CortexR52x1 master port flash[1]; master port amba[1]; slave port ext_slave; + slave port core_reset[1]; + slave port poweron_reset[1]; + slave port halt[1]; + slave port top_reset; slave port clock_rate_s { diff --git a/src/arch/arm/fastmodel/CortexR52/x2/x2.lisa b/src/arch/arm/fastmodel/CortexR52/x2/x2.lisa index bcbf1f4538..9b992a4d37 100644 --- a/src/arch/arm/fastmodel/CortexR52/x2/x2.lisa +++ b/src/arch/arm/fastmodel/CortexR52/x2/x2.lisa @@ -45,6 +45,10 @@ component CortexR52x2 core.flash_m => self.flash; core.pvbus_core_m => self.amba; self.ext_slave => core.ext_slave_s; + self.core_reset => core.reset; + self.poweron_reset => core.cpuporeset; + self.top_reset => core.topreset; + self.halt => core.cpuhalt; // Clocks. clock1Hz.clk_out => clockDiv.clk_in; @@ -67,6 +71,10 @@ component CortexR52x2 master port flash[2]; master port amba[2]; slave port ext_slave; + slave port core_reset[2]; + slave port poweron_reset[2]; + slave port halt[2]; + slave port top_reset; slave port clock_rate_s { diff --git a/src/arch/arm/fastmodel/CortexR52/x3/x3.lisa b/src/arch/arm/fastmodel/CortexR52/x3/x3.lisa index 3d63bbfc25..18619b9a99 100644 --- a/src/arch/arm/fastmodel/CortexR52/x3/x3.lisa +++ b/src/arch/arm/fastmodel/CortexR52/x3/x3.lisa @@ -45,6 +45,10 @@ component CortexR52x3 core.flash_m => self.flash; core.pvbus_core_m => self.amba; self.ext_slave => core.ext_slave_s; + self.core_reset => core.reset; + self.poweron_reset => core.cpuporeset; + self.top_reset => core.topreset; + self.halt => core.cpuhalt; // Clocks. clock1Hz.clk_out => clockDiv.clk_in; @@ -68,6 +72,10 @@ component CortexR52x3 master port flash[3]; master port amba[3]; slave port ext_slave; + slave port core_reset[3]; + slave port poweron_reset[3]; + slave port halt[3]; + slave port top_reset; slave port clock_rate_s { diff --git a/src/arch/arm/fastmodel/CortexR52/x4/x4.lisa b/src/arch/arm/fastmodel/CortexR52/x4/x4.lisa index 6443383f7f..d22079f336 100644 --- a/src/arch/arm/fastmodel/CortexR52/x4/x4.lisa +++ b/src/arch/arm/fastmodel/CortexR52/x4/x4.lisa @@ -45,6 +45,10 @@ component CortexR52x4 core.flash_m => self.flash; core.pvbus_core_m => self.amba; self.ext_slave => core.ext_slave_s; + self.core_reset => core.reset; + self.poweron_reset => core.cpuporeset; + self.top_reset => core.topreset; + self.halt => core.cpuhalt; // Clocks. clock1Hz.clk_out => clockDiv.clk_in; @@ -69,6 +73,10 @@ component CortexR52x4 master port flash[4]; master port amba[4]; slave port ext_slave; + slave port core_reset[4]; + slave port poweron_reset[4]; + slave port halt[4]; + slave port top_reset; slave port clock_rate_s {