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Add default value and change Ruby address format specifier

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Change-Id: I8fbaf34745e90589e610d3b9bd423937e7ebdc3d
This commit is contained in:
Jarvis Jia
2024-06-17 03:27:25 -05:00
parent edb2e76077
commit 3a2bf47d57
2 changed files with 6 additions and 6 deletions
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4
src/mem/ruby/protocol/GPU_VIPER-TCC.sm
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@@ -655,12 +655,12 @@ machine(MachineType:TCC, "TCC Cache")
action(p_profileMiss, "pm", desc="Profile cache miss") {
L2cache.profileDemandMiss();
DPRINTF(RubyHitMiss, "in TCC miss at %p \n", address);
DPRINTF(RubyHitMiss, "in TCC miss at %#lx\n", address);
}
action(p_profileHit, "ph", desc="Profile cache hit") {
L2cache.profileDemandHit();
DPRINTF(RubyHitMiss, "in TCC hit at %p \n", address);
DPRINTF(RubyHitMiss, "in TCC hit at %#lx\n", address);
}
action(t_allocateTBE, "t", desc="allocate TBE Entry") {

8
src/mem/ruby/system/GPUCoalescer.hh
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@@ -292,7 +292,7 @@ class GPUCoalescer : public RubyPort
void readCallback(Addr address,
MachineType mach,
DataBlock& data,
bool externalHit);
bool externalHit = false);
void readCallback(Addr address,
MachineType mach,
@@ -300,7 +300,7 @@ class GPUCoalescer : public RubyPort
Cycles initialRequestTime,
Cycles forwardRequestTime,
Cycles firstResponseTime,
bool externalHit);
bool externalHit = false);
void readCallback(Addr address,
MachineType mach,
@@ -309,7 +309,7 @@ class GPUCoalescer : public RubyPort
Cycles forwardRequestTime,
Cycles firstResponseTime,
bool isRegion,
bool externalHit);
bool externalHit = false);
/* atomics need their own callback because the data
might be const coming from SLICC */
@@ -396,7 +396,7 @@ class GPUCoalescer : public RubyPort
Cycles forwardRequestTime,
Cycles firstResponseTime,
bool isRegion,
bool externalHit);
bool externalHit = false);
void recordMissLatency(CoalescedRequest* crequest,
MachineType mach,