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arch-arm: Use MAIR_EL2 mem attribute register when in EL0 host

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With the old code, the MAIR_EL1 register was checked when inserting
an EL2&0 TLB entry

Change-Id: I064032fb2946777c2f4c50c06a124f828245e18a
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
This commit is contained in:
Giacomo Travaglini
2024-01-03 17:35:14 +00:00
parent d42ef792bf
commit 3737e8b6df
1 changed files with 5 additions and 6 deletions
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11
src/arch/arm/table_walker.cc
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@@ -1560,19 +1560,18 @@ TableWalker::memAttrsAArch64(ThreadContext *tc, TlbEntry &te,
uint8_t attrIndx = l_descriptor.attrIndx(); uint8_t attrIndx = l_descriptor.attrIndx();
DPRINTF(TLBVerbose, "memAttrsAArch64 AttrIndx:%#x sh:%#x\n", attrIndx, sh); DPRINTF(TLBVerbose, "memAttrsAArch64 AttrIndx:%#x sh:%#x\n", attrIndx, sh);
ExceptionLevel regime = s1TranslationRegime(tc, currState->el);
// Select MAIR // Select MAIR
uint64_t mair; uint64_t mair;
switch (regime) { switch (currState->regime) {
case EL0: case TranslationRegime::EL10:
case EL1:
mair = tc->readMiscReg(MISCREG_MAIR_EL1); mair = tc->readMiscReg(MISCREG_MAIR_EL1);
break; break;
case EL2: case TranslationRegime::EL20:
case TranslationRegime::EL2:
mair = tc->readMiscReg(MISCREG_MAIR_EL2); mair = tc->readMiscReg(MISCREG_MAIR_EL2);
break; break;
case EL3: case TranslationRegime::EL3:
mair = tc->readMiscReg(MISCREG_MAIR_EL3); mair = tc->readMiscReg(MISCREG_MAIR_EL3);
break; break;
default: default: