From 3737e8b6dfc67cd41ef1ebfdbe191133cbd23e4b Mon Sep 17 00:00:00 2001 From: Giacomo Travaglini Date: Wed, 3 Jan 2024 17:35:14 +0000 Subject: [PATCH] arch-arm: Use MAIR_EL2 mem attribute register when in EL0 host With the old code, the MAIR_EL1 register was checked when inserting an EL2&0 TLB entry Change-Id: I064032fb2946777c2f4c50c06a124f828245e18a Signed-off-by: Giacomo Travaglini --- src/arch/arm/table_walker.cc | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/src/arch/arm/table_walker.cc b/src/arch/arm/table_walker.cc index 4ae18b3b83..077abe653e 100644 --- a/src/arch/arm/table_walker.cc +++ b/src/arch/arm/table_walker.cc @@ -1560,19 +1560,18 @@ TableWalker::memAttrsAArch64(ThreadContext *tc, TlbEntry &te, uint8_t attrIndx = l_descriptor.attrIndx(); DPRINTF(TLBVerbose, "memAttrsAArch64 AttrIndx:%#x sh:%#x\n", attrIndx, sh); - ExceptionLevel regime = s1TranslationRegime(tc, currState->el); // Select MAIR uint64_t mair; - switch (regime) { - case EL0: - case EL1: + switch (currState->regime) { + case TranslationRegime::EL10: mair = tc->readMiscReg(MISCREG_MAIR_EL1); break; - case EL2: + case TranslationRegime::EL20: + case TranslationRegime::EL2: mair = tc->readMiscReg(MISCREG_MAIR_EL2); break; - case EL3: + case TranslationRegime::EL3: mair = tc->readMiscReg(MISCREG_MAIR_EL3); break; default: