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mem-ruby, gpu-compute: fix GPU SQC/TCP Ruby formatting (#538)

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mem-ruby, gpu-compute: fix GPU SQC/TCP Ruby formatting

Fix several not properly indented prints and extraneous extra lines in
the SLICC code for the GPU SQC (L1I$) and TCP (L1D$).
This commit is contained in:
Matt Sinclair
2023-11-13 16:20:54 -06:00
committed by GitHub
parent b62308dfa3
commit 3642bc4892
2 changed files with 13 additions and 14 deletions
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2
src/mem/ruby/protocol/GPU_VIPER-SQC.sm
View File

@@ -75,7 +75,7 @@ machine(MachineType:SQC, "GPU SQC (L1 I Cache)")
}
structure(TBE, desc="...") {
State TBEState, desc="Transient state";
State TBEState, desc="Transient state";
DataBlock DataBlk, desc="data for the block, required for concurrent writebacks";
bool Dirty, desc="Is the data dirty (different than memory)?";
int NumPendingMsgs, desc="Number of acks/data messages that this processor is waiting for";

25
src/mem/ruby/protocol/GPU_VIPER-TCP.sm
View File

@@ -52,30 +52,30 @@ machine(MachineType:TCP, "GPU TCP (L1 Data Cache)")
{
state_declaration(State, desc="TCP Cache States", default="TCP_State_I") {
I, AccessPermission:Invalid, desc="Invalid";
I, AccessPermission:Invalid, desc="Invalid";
V, AccessPermission:Read_Only, desc="Valid";
A, AccessPermission:Invalid, desc="Waiting on Atomic";
A, AccessPermission:Invalid, desc="Waiting on Atomic";
F, AccessPermission:Invalid, desc="Flushing; Waiting for Ack";
}
enumeration(Event, desc="TCP Events") {
// Core initiated
Load, desc="Load";
Load, desc="Load";
LoadBypassEvict, desc="Bypass L1 on a load. Evict if cache block already allocated";
Store, desc="Store to L1 (L1 is dirty)";
StoreThrough, desc="Store directly to L2(L1 is clean)";
Atomic, desc="Atomic";
Flush, desc="Flush if dirty(wbL1 for Store Release)";
Evict, desc="Evict if clean(invL1 for Load Acquire)";
Store, desc="Store to L1 (L1 is dirty)";
StoreThrough, desc="Store directly to L2(L1 is clean)";
Atomic, desc="Atomic";
Flush, desc="Flush if dirty(wbL1 for Store Release)";
Evict, desc="Evict if clean(invL1 for Load Acquire)";
// Mem sys initiated
Repl, desc="Replacing block from cache";
Repl, desc="Replacing block from cache";
// TCC initiated
TCC_Ack, desc="TCC Ack to Core Request";
TCC_AckWB, desc="TCC Ack for WB";
TCC_Ack, desc="TCC Ack to Core Request";
TCC_AckWB, desc="TCC Ack for WB";
// Disable L1 cache
Bypass, desc="Bypass the entire L1 cache";
Bypass, desc="Bypass the entire L1 cache";
}
enumeration(RequestType,
@@ -613,7 +613,6 @@ machine(MachineType:TCP, "GPU TCP (L1 Data Cache)")
L1cache.profileDemandHit();
}
// Transitions
// ArrayRead/Write assumptions:
// All requests read Tag Array