3642bc4892
mem-ruby, gpu-compute: fix GPU SQC/TCP Ruby formatting Fix several not properly indented prints and extraneous extra lines in the SLICC code for the GPU SQC (L1I$) and TCP (L1D$).
763 lines
26 KiB
Plaintext
763 lines
26 KiB
Plaintext
/*
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* Copyright (c) 2011-2015 Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* Author: Blake Hechtman
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*/
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machine(MachineType:TCP, "GPU TCP (L1 Data Cache)")
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: VIPERCoalescer* coalescer;
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Sequencer* sequencer;
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bool use_seq_not_coal;
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CacheMemory * L1cache;
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bool WB; /*is this cache Writeback?*/
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bool disableL1; /* bypass L1 cache? */
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int TCC_select_num_bits;
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Cycles issue_latency := 40; // time to send data down to TCC
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Cycles l2_hit_latency := 18;
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MessageBuffer * requestFromTCP, network="To", virtual_network="1", vnet_type="request";
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MessageBuffer * responseFromTCP, network="To", virtual_network="3", vnet_type="response";
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MessageBuffer * unblockFromCore, network="To", virtual_network="5", vnet_type="unblock";
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MessageBuffer * probeToTCP, network="From", virtual_network="1", vnet_type="request";
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MessageBuffer * responseToTCP, network="From", virtual_network="3", vnet_type="response";
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MessageBuffer * mandatoryQueue;
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{
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state_declaration(State, desc="TCP Cache States", default="TCP_State_I") {
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I, AccessPermission:Invalid, desc="Invalid";
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V, AccessPermission:Read_Only, desc="Valid";
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A, AccessPermission:Invalid, desc="Waiting on Atomic";
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F, AccessPermission:Invalid, desc="Flushing; Waiting for Ack";
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}
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enumeration(Event, desc="TCP Events") {
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// Core initiated
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Load, desc="Load";
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LoadBypassEvict, desc="Bypass L1 on a load. Evict if cache block already allocated";
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Store, desc="Store to L1 (L1 is dirty)";
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StoreThrough, desc="Store directly to L2(L1 is clean)";
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Atomic, desc="Atomic";
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Flush, desc="Flush if dirty(wbL1 for Store Release)";
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Evict, desc="Evict if clean(invL1 for Load Acquire)";
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// Mem sys initiated
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Repl, desc="Replacing block from cache";
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// TCC initiated
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TCC_Ack, desc="TCC Ack to Core Request";
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TCC_AckWB, desc="TCC Ack for WB";
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// Disable L1 cache
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Bypass, desc="Bypass the entire L1 cache";
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}
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enumeration(RequestType,
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desc="To communicate stats from transitions to recordStats") {
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DataArrayRead, desc="Read the data array";
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DataArrayWrite, desc="Write the data array";
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TagArrayRead, desc="Read the data array";
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TagArrayWrite, desc="Write the data array";
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TagArrayFlash, desc="Flash clear the data array";
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}
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structure(Entry, desc="...", interface="AbstractCacheEntry") {
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State CacheState, desc="cache state";
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bool Dirty, desc="Is the data dirty (diff than memory)?";
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DataBlock DataBlk, desc="data for the block";
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bool FromL2, default="false", desc="block just moved from L2";
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WriteMask writeMask, desc="written bytes masks";
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}
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structure(TBE, desc="...") {
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State TBEState, desc="Transient state";
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DataBlock DataBlk, desc="data for the block, required for concurrent writebacks";
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bool Dirty, desc="Is the data dirty (different than memory)?";
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int NumPendingMsgs,desc="Number of acks/data messages that this processor is waiting for";
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bool Shared, desc="Victim hit by shared probe";
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}
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structure(TBETable, external="yes") {
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TBE lookup(Addr);
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void allocate(Addr);
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void deallocate(Addr);
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bool isPresent(Addr);
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}
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TBETable TBEs, template="<TCP_TBE>", constructor="m_number_of_TBEs";
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int TCC_select_low_bit, default="RubySystem::getBlockSizeBits()";
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int WTcnt, default="0";
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int Fcnt, default="0";
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bool inFlush, default="false";
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void set_cache_entry(AbstractCacheEntry b);
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void unset_cache_entry();
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void set_tbe(TBE b);
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void unset_tbe();
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void wakeUpAllBuffers();
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void wakeUpBuffers(Addr a);
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Cycles curCycle();
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// Internal functions
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Tick clockEdge();
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Tick cyclesToTicks(Cycles c);
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Entry getCacheEntry(Addr address), return_by_pointer="yes" {
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Entry cache_entry := static_cast(Entry, "pointer", L1cache.lookup(address));
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return cache_entry;
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}
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DataBlock getDataBlock(Addr addr), return_by_ref="yes" {
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TBE tbe := TBEs.lookup(addr);
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if(is_valid(tbe)) {
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return tbe.DataBlk;
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} else {
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return getCacheEntry(addr).DataBlk;
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}
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}
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State getState(TBE tbe, Entry cache_entry, Addr addr) {
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if (is_valid(tbe)) {
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return tbe.TBEState;
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} else if (is_valid(cache_entry)) {
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return cache_entry.CacheState;
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}
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return State:I;
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}
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void setState(TBE tbe, Entry cache_entry, Addr addr, State state) {
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if (is_valid(tbe)) {
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tbe.TBEState := state;
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}
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if (is_valid(cache_entry)) {
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cache_entry.CacheState := state;
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}
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}
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void functionalRead(Addr addr, Packet *pkt) {
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TBE tbe := TBEs.lookup(addr);
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if(is_valid(tbe)) {
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testAndRead(addr, tbe.DataBlk, pkt);
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} else {
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functionalMemoryRead(pkt);
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}
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}
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int functionalWrite(Addr addr, Packet *pkt) {
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int num_functional_writes := 0;
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TBE tbe := TBEs.lookup(addr);
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if(is_valid(tbe)) {
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num_functional_writes := num_functional_writes +
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testAndWrite(addr, tbe.DataBlk, pkt);
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}
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num_functional_writes := num_functional_writes +
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functionalMemoryWrite(pkt);
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return num_functional_writes;
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}
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AccessPermission getAccessPermission(Addr addr) {
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TBE tbe := TBEs.lookup(addr);
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if(is_valid(tbe)) {
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return TCP_State_to_permission(tbe.TBEState);
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}
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Entry cache_entry := getCacheEntry(addr);
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if(is_valid(cache_entry)) {
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return TCP_State_to_permission(cache_entry.CacheState);
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}
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return AccessPermission:NotPresent;
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}
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bool isValid(Addr addr) {
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AccessPermission perm := getAccessPermission(addr);
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if (perm == AccessPermission:NotPresent ||
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perm == AccessPermission:Invalid ||
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perm == AccessPermission:Busy) {
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return false;
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} else {
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return true;
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}
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}
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void setAccessPermission(Entry cache_entry, Addr addr, State state) {
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if (is_valid(cache_entry)) {
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cache_entry.changePermission(TCP_State_to_permission(state));
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}
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}
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void recordRequestType(RequestType request_type, Addr addr) {
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if (request_type == RequestType:DataArrayRead) {
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L1cache.recordRequestType(CacheRequestType:DataArrayRead, addr);
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} else if (request_type == RequestType:DataArrayWrite) {
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L1cache.recordRequestType(CacheRequestType:DataArrayWrite, addr);
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} else if (request_type == RequestType:TagArrayRead) {
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L1cache.recordRequestType(CacheRequestType:TagArrayRead, addr);
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} else if (request_type == RequestType:TagArrayFlash) {
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L1cache.recordRequestType(CacheRequestType:TagArrayRead, addr);
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} else if (request_type == RequestType:TagArrayWrite) {
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L1cache.recordRequestType(CacheRequestType:TagArrayWrite, addr);
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}
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}
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bool checkResourceAvailable(RequestType request_type, Addr addr) {
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if (request_type == RequestType:DataArrayRead) {
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return L1cache.checkResourceAvailable(CacheResourceType:DataArray, addr);
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} else if (request_type == RequestType:DataArrayWrite) {
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return L1cache.checkResourceAvailable(CacheResourceType:DataArray, addr);
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} else if (request_type == RequestType:TagArrayRead) {
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return L1cache.checkResourceAvailable(CacheResourceType:TagArray, addr);
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} else if (request_type == RequestType:TagArrayWrite) {
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return L1cache.checkResourceAvailable(CacheResourceType:TagArray, addr);
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} else if (request_type == RequestType:TagArrayFlash) {
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// FIXME should check once per cache, rather than once per cacheline
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return L1cache.checkResourceAvailable(CacheResourceType:TagArray, addr);
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} else {
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error("Invalid RequestType type in checkResourceAvailable");
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return true;
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}
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}
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// Out Ports
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out_port(requestNetwork_out, CPURequestMsg, requestFromTCP);
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// In Ports
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in_port(responseToTCP_in, ResponseMsg, responseToTCP) {
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if (responseToTCP_in.isReady(clockEdge())) {
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peek(responseToTCP_in, ResponseMsg, block_on="addr") {
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Entry cache_entry := getCacheEntry(in_msg.addr);
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TBE tbe := TBEs.lookup(in_msg.addr);
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DPRINTF(RubySlicc, "In responseToTCP_in with %s\n", in_msg);
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if (in_msg.Type == CoherenceResponseType:TDSysResp) {
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if (disableL1 || in_msg.isGLCSet || in_msg.isSLCSet) {
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// If L1 is disabled or requests have GLC or SLC flag set,
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// then, the requests should not cache in the L1. The response
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// from L2/global memory should bypass the cache
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trigger(Event:Bypass, in_msg.addr, cache_entry, tbe);
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} else {
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if (is_valid(cache_entry) || L1cache.cacheAvail(in_msg.addr)) {
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trigger(Event:TCC_Ack, in_msg.addr, cache_entry, tbe);
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} else {
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Addr victim := L1cache.cacheProbe(in_msg.addr);
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trigger(Event:Repl, victim, getCacheEntry(victim), TBEs.lookup(victim));
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}
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}
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} else if (in_msg.Type == CoherenceResponseType:TDSysWBAck ||
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in_msg.Type == CoherenceResponseType:NBSysWBAck) {
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trigger(Event:TCC_AckWB, in_msg.addr, cache_entry, tbe);
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DPRINTF(RubySlicc, "Issuing TCC_AckWB\n");
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} else {
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error("Unexpected Response Message to Core");
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}
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}
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}
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}
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in_port(mandatoryQueue_in, RubyRequest, mandatoryQueue, desc="...") {
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if (mandatoryQueue_in.isReady(clockEdge())) {
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peek(mandatoryQueue_in, RubyRequest, block_on="LineAddress") {
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Entry cache_entry := getCacheEntry(in_msg.LineAddress);
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TBE tbe := TBEs.lookup(in_msg.LineAddress);
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DPRINTF(RubySlicc, "%s\n", in_msg);
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if (in_msg.Type == RubyRequestType:LD) {
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if ((in_msg.isGLCSet || in_msg.isSLCSet) && is_valid(cache_entry)) {
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// Read requests with GLC or SLC bit set should not cache in the L1.
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// They need to bypass the L1 and go to the L2. If an entry exists
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// in the L1, it needs to be evicted
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trigger(Event:LoadBypassEvict, in_msg.LineAddress, cache_entry, tbe);
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}
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else {
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trigger(Event:Load, in_msg.LineAddress, cache_entry, tbe);
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}
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} else if (in_msg.Type == RubyRequestType:ATOMIC ||
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in_msg.Type == RubyRequestType:ATOMIC_RETURN ||
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in_msg.Type == RubyRequestType:ATOMIC_NO_RETURN) {
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trigger(Event:Atomic, in_msg.LineAddress, cache_entry, tbe);
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} else if (in_msg.Type == RubyRequestType:ST) {
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if(disableL1 || in_msg.isGLCSet || in_msg.isSLCSet) {
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// Write requests with GLC or SLC bit set, or when L1 is disabled,
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// should not cache in the L1. They need to perform a store through
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trigger(Event:StoreThrough, in_msg.LineAddress, cache_entry, tbe);
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} else {
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if (is_valid(cache_entry) || L1cache.cacheAvail(in_msg.LineAddress)) {
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trigger(Event:StoreThrough, in_msg.LineAddress, cache_entry, tbe);
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} else {
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Addr victim := L1cache.cacheProbe(in_msg.LineAddress);
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trigger(Event:Repl, victim, getCacheEntry(victim), TBEs.lookup(victim));
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}
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} // end if (disableL1)
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} else if (in_msg.Type == RubyRequestType:FLUSH) {
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trigger(Event:Flush, in_msg.LineAddress, cache_entry, tbe);
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} else if (in_msg.Type == RubyRequestType:REPLACEMENT){
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trigger(Event:Evict, in_msg.LineAddress, cache_entry, tbe);
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} else {
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error("Unexpected Request Message from VIC");
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}
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}
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}
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}
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// Actions
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action(ic_invCache, "ic", desc="invalidate cache") {
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if(is_valid(cache_entry)) {
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cache_entry.writeMask.clear();
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L1cache.deallocate(address);
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}
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unset_cache_entry();
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}
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action(n_issueRdBlk, "n", desc="Issue RdBlk") {
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enqueue(requestNetwork_out, CPURequestMsg, issue_latency) {
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out_msg.addr := address;
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out_msg.Type := CoherenceRequestType:RdBlk;
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out_msg.Requestor := machineID;
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out_msg.Destination.add(mapAddressToRange(address,MachineType:TCC,
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TCC_select_low_bit, TCC_select_num_bits));
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out_msg.MessageSize := MessageSizeType:Request_Control;
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out_msg.InitialRequestTime := curCycle();
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peek(mandatoryQueue_in, RubyRequest) {
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out_msg.isGLCSet := in_msg.isGLCSet;
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out_msg.isSLCSet := in_msg.isSLCSet;
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}
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}
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}
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action(rb_bypassDone, "rb", desc="bypass L1 of read access") {
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peek(responseToTCP_in, ResponseMsg) {
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DataBlock tmp:= in_msg.DataBlk;
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if (use_seq_not_coal) {
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sequencer.readCallback(address, tmp, false, MachineType:L1Cache);
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} else {
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coalescer.readCallback(address, MachineType:L1Cache, tmp);
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}
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if(is_valid(cache_entry)) {
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unset_cache_entry();
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}
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}
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}
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action(wab_bypassDone, "wab", desc="bypass L1 of write access") {
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peek(responseToTCP_in, ResponseMsg) {
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DataBlock tmp := in_msg.DataBlk;
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if (use_seq_not_coal) {
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sequencer.writeCallback(address, tmp, false, MachineType:L1Cache);
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} else {
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coalescer.writeCallback(address, MachineType:L1Cache, tmp);
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}
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}
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}
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action(norl_issueRdBlkOrloadDone, "norl", desc="local load done") {
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peek(mandatoryQueue_in, RubyRequest){
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if (cache_entry.writeMask.containsMask(in_msg.writeMask)) {
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if (use_seq_not_coal) {
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sequencer.readCallback(address, cache_entry.DataBlk, false, MachineType:L1Cache);
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} else {
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coalescer.readCallback(address, MachineType:L1Cache, cache_entry.DataBlk);
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}
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} else {
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enqueue(requestNetwork_out, CPURequestMsg, issue_latency) {
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out_msg.addr := address;
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out_msg.Type := CoherenceRequestType:RdBlk;
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out_msg.Requestor := machineID;
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out_msg.Destination.add(mapAddressToRange(address,MachineType:TCC,
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TCC_select_low_bit, TCC_select_num_bits));
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out_msg.MessageSize := MessageSizeType:Request_Control;
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out_msg.InitialRequestTime := curCycle();
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out_msg.isGLCSet := in_msg.isGLCSet;
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out_msg.isSLCSet := in_msg.isSLCSet;
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}
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}
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}
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}
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action(wt_writeThrough, "wt", desc="Flush dirty data") {
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WTcnt := WTcnt + 1;
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APPEND_TRANSITION_COMMENT("write++ = ");
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APPEND_TRANSITION_COMMENT(WTcnt);
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enqueue(requestNetwork_out, CPURequestMsg, issue_latency) {
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out_msg.addr := address;
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out_msg.Requestor := machineID;
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assert(is_valid(cache_entry));
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out_msg.DataBlk := cache_entry.DataBlk;
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out_msg.writeMask.clear();
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out_msg.writeMask.orMask(cache_entry.writeMask);
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out_msg.Destination.add(mapAddressToRange(address,MachineType:TCC,
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TCC_select_low_bit, TCC_select_num_bits));
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out_msg.MessageSize := MessageSizeType:Data;
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out_msg.Type := CoherenceRequestType:WriteThrough;
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out_msg.InitialRequestTime := curCycle();
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out_msg.Shared := false;
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// forward inst sequence number to lower TCC
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peek(mandatoryQueue_in, RubyRequest) {
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out_msg.instSeqNum := in_msg.instSeqNum;
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out_msg.isGLCSet := in_msg.isGLCSet;
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out_msg.isSLCSet := in_msg.isSLCSet;
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}
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}
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}
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action(at_atomicThrough, "at", desc="send Atomic") {
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peek(mandatoryQueue_in, RubyRequest) {
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enqueue(requestNetwork_out, CPURequestMsg, issue_latency) {
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out_msg.addr := address;
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out_msg.Requestor := machineID;
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out_msg.writeMask.clear();
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out_msg.writeMask.orMask(in_msg.writeMask);
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out_msg.Destination.add(mapAddressToRange(address,MachineType:TCC,
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TCC_select_low_bit, TCC_select_num_bits));
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out_msg.MessageSize := MessageSizeType:Data;
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out_msg.Type := CoherenceRequestType:Atomic;
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out_msg.InitialRequestTime := curCycle();
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out_msg.Shared := false;
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peek(mandatoryQueue_in, RubyRequest) {
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out_msg.instSeqNum := in_msg.instSeqNum;
|
|
out_msg.isGLCSet := in_msg.isGLCSet;
|
|
out_msg.isSLCSet := in_msg.isSLCSet;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
action(a_allocate, "a", desc="allocate block") {
|
|
if (is_invalid(cache_entry)) {
|
|
set_cache_entry(L1cache.allocate(address, new Entry));
|
|
}
|
|
cache_entry.writeMask.clear();
|
|
}
|
|
|
|
action(t_allocateTBE, "t", desc="allocate TBE Entry") {
|
|
check_allocate(TBEs);
|
|
TBEs.allocate(address);
|
|
set_tbe(TBEs.lookup(address));
|
|
}
|
|
|
|
action(d_deallocateTBE, "d", desc="Deallocate TBE") {
|
|
TBEs.deallocate(address);
|
|
unset_tbe();
|
|
}
|
|
|
|
action(sf_setFlush, "sf", desc="set flush") {
|
|
inFlush := true;
|
|
APPEND_TRANSITION_COMMENT(" inFlush is true");
|
|
enqueue(requestNetwork_out, CPURequestMsg, issue_latency) {
|
|
out_msg.addr := address;
|
|
out_msg.Requestor := machineID;
|
|
assert(is_valid(cache_entry));
|
|
out_msg.DataBlk := cache_entry.DataBlk;
|
|
out_msg.writeMask.clear();
|
|
out_msg.writeMask.orMask(cache_entry.writeMask);
|
|
out_msg.Destination.add(mapAddressToRange(address,MachineType:TCC,
|
|
TCC_select_low_bit, TCC_select_num_bits));
|
|
out_msg.MessageSize := MessageSizeType:Data;
|
|
out_msg.Type := CoherenceRequestType:WriteFlush;
|
|
out_msg.InitialRequestTime := curCycle();
|
|
out_msg.Shared := false;
|
|
out_msg.isSLCSet := false;
|
|
peek(mandatoryQueue_in, RubyRequest) {
|
|
out_msg.instSeqNum := in_msg.instSeqNum;
|
|
}
|
|
}
|
|
}
|
|
|
|
action(p_popMandatoryQueue, "pm", desc="Pop Mandatory Queue") {
|
|
mandatoryQueue_in.dequeue(clockEdge());
|
|
}
|
|
|
|
action(pr_popResponseQueue, "pr", desc="Pop Response Queue") {
|
|
responseToTCP_in.dequeue(clockEdge());
|
|
}
|
|
|
|
action(l_loadDoneHit, "ldh", desc="local load done (hits in TCP)") {
|
|
assert(is_valid(cache_entry));
|
|
if (use_seq_not_coal) {
|
|
sequencer.readCallback(address, cache_entry.DataBlk, true, MachineType:L1Cache);
|
|
} else {
|
|
coalescer.readCallback(address, MachineType:L1Cache, cache_entry.DataBlk);
|
|
}
|
|
}
|
|
|
|
action(l_loadDoneMiss, "ldm", desc="local load done (misses in TCP)") {
|
|
assert(is_valid(cache_entry));
|
|
if (use_seq_not_coal) {
|
|
sequencer.readCallback(address, cache_entry.DataBlk, false, MachineType:L1Cache);
|
|
} else {
|
|
coalescer.readCallback(address, MachineType:L1Cache, cache_entry.DataBlk);
|
|
}
|
|
}
|
|
|
|
action(ad_atomicDone, "ad", desc="atomic done") {
|
|
assert(is_valid(cache_entry));
|
|
coalescer.atomicCallback(address, MachineType:L1Cache, cache_entry.DataBlk);
|
|
}
|
|
|
|
action(s_storeDoneHit, "sdh", desc="local store done (hits in TCP)") {
|
|
assert(is_valid(cache_entry));
|
|
|
|
if (use_seq_not_coal) {
|
|
sequencer.writeCallback(address, cache_entry.DataBlk, true, MachineType:L1Cache);
|
|
} else {
|
|
coalescer.writeCallback(address, MachineType:L1Cache, cache_entry.DataBlk);
|
|
}
|
|
cache_entry.Dirty := true;
|
|
}
|
|
|
|
action(s_storeDoneMiss, "sdm", desc="local store done (misses in TCP)") {
|
|
assert(is_valid(cache_entry));
|
|
|
|
if (use_seq_not_coal) {
|
|
sequencer.writeCallback(address, cache_entry.DataBlk, false, MachineType:L1Cache);
|
|
} else {
|
|
coalescer.writeCallback(address, MachineType:L1Cache, cache_entry.DataBlk);
|
|
}
|
|
cache_entry.Dirty := true;
|
|
}
|
|
|
|
action(f_flushDone, "f", desc="flush done") {
|
|
assert(is_valid(cache_entry));
|
|
|
|
if (use_seq_not_coal) {
|
|
sequencer.writeCallback(address, cache_entry.DataBlk, false, MachineType:L1Cache);
|
|
} else {
|
|
coalescer.writeCallback(address, MachineType:L1Cache, cache_entry.DataBlk);
|
|
}
|
|
}
|
|
|
|
action(inv_invDone, "inv", desc="local inv done") {
|
|
if (use_seq_not_coal) {
|
|
DPRINTF(RubySlicc, "Sequencer does not define invCallback!\n");
|
|
assert(false);
|
|
} else {
|
|
coalescer.invTCPCallback(address);
|
|
}
|
|
}
|
|
|
|
action(wd_wtDone, "wd", desc="writethrough done") {
|
|
if (use_seq_not_coal) {
|
|
DPRINTF(RubySlicc, "Sequencer does not define writeCompleteCallback!\n");
|
|
assert(false);
|
|
} else {
|
|
peek(responseToTCP_in, ResponseMsg) {
|
|
coalescer.writeCompleteCallback(address, in_msg.instSeqNum);
|
|
}
|
|
}
|
|
}
|
|
|
|
action(dw_dirtyWrite, "dw", desc="update write mask"){
|
|
peek(mandatoryQueue_in, RubyRequest) {
|
|
cache_entry.DataBlk.copyPartial(in_msg.WTData,in_msg.writeMask);
|
|
cache_entry.writeMask.orMask(in_msg.writeMask);
|
|
}
|
|
}
|
|
action(w_writeCache, "w", desc="write data to cache") {
|
|
peek(responseToTCP_in, ResponseMsg) {
|
|
assert(is_valid(cache_entry));
|
|
DataBlock tmp := in_msg.DataBlk;
|
|
tmp.copyPartial(cache_entry.DataBlk,cache_entry.writeMask);
|
|
cache_entry.DataBlk := tmp;
|
|
}
|
|
}
|
|
|
|
action(mru_updateMRU, "mru", desc="Touch block for replacement policy") {
|
|
L1cache.setMRU(address);
|
|
}
|
|
|
|
// action(zz_recycleMandatoryQueue, "\z", desc="recycle mandatory queue") {
|
|
// mandatoryQueue_in.recycle(clockEdge(), cyclesToTicks(recycle_latency));
|
|
// }
|
|
|
|
action(z_stall, "z", desc="stall; built-in") {
|
|
// built-int action
|
|
}
|
|
|
|
// added for profiling
|
|
action(uu_profileDataMiss, "\udm", desc="Profile the demand miss"){
|
|
L1cache.profileDemandMiss();
|
|
}
|
|
|
|
action(uu_profileDataHit, "\udh", desc="Profile the demand hit"){
|
|
L1cache.profileDemandHit();
|
|
}
|
|
|
|
// Transitions
|
|
// ArrayRead/Write assumptions:
|
|
// All requests read Tag Array
|
|
// TBE allocation write the TagArray to I
|
|
// TBE only checked on misses
|
|
// Stores will also write dirty bits in the tag
|
|
// WriteThroughs still need to use cache entry as staging buffer for wavefront
|
|
|
|
// Stalling transitions do NOT check the tag array...and if they do,
|
|
// they can cause a resource stall deadlock!
|
|
|
|
transition({A}, {Load, Atomic, StoreThrough}) { //TagArrayRead} {
|
|
z_stall;
|
|
}
|
|
|
|
transition(I, Load) {TagArrayRead} {
|
|
n_issueRdBlk;
|
|
uu_profileDataMiss;
|
|
p_popMandatoryQueue;
|
|
}
|
|
|
|
transition(V, Load) {TagArrayRead, DataArrayRead} {
|
|
l_loadDoneHit;
|
|
mru_updateMRU;
|
|
uu_profileDataHit;
|
|
p_popMandatoryQueue;
|
|
}
|
|
|
|
// Transition to be called when a load request with GLC or SLC flag set arrives
|
|
// at L1. This transition invalidates any existing entry and forwards the
|
|
// request to L2.
|
|
transition(V, LoadBypassEvict, I) {TagArrayRead, TagArrayWrite} {
|
|
uu_profileDataMiss;
|
|
ic_invCache;
|
|
n_issueRdBlk;
|
|
p_popMandatoryQueue;
|
|
}
|
|
|
|
// Transition to be called when a load request with GLC or SLC flag set arrives
|
|
// at L1. Since the entry is invalid, there isn't anything to forward to L2,
|
|
// so just issue read.
|
|
transition(I, LoadBypassEvict) {TagArrayRead, TagArrayWrite} {
|
|
uu_profileDataMiss;
|
|
n_issueRdBlk;
|
|
p_popMandatoryQueue;
|
|
}
|
|
|
|
transition({V, I}, Atomic, A) {TagArrayRead, TagArrayWrite} {
|
|
t_allocateTBE;
|
|
mru_updateMRU;
|
|
at_atomicThrough;
|
|
p_popMandatoryQueue;
|
|
}
|
|
|
|
transition(I, StoreThrough) {TagArrayRead, TagArrayWrite, DataArrayWrite} {
|
|
a_allocate;
|
|
dw_dirtyWrite;
|
|
s_storeDoneMiss;
|
|
uu_profileDataMiss;
|
|
wt_writeThrough;
|
|
ic_invCache;
|
|
p_popMandatoryQueue;
|
|
}
|
|
|
|
transition(V, StoreThrough, I) {TagArrayRead, TagArrayWrite, DataArrayWrite} {
|
|
dw_dirtyWrite;
|
|
s_storeDoneHit;
|
|
uu_profileDataHit;
|
|
wt_writeThrough;
|
|
ic_invCache;
|
|
p_popMandatoryQueue;
|
|
}
|
|
|
|
transition(I, TCC_Ack, V) {TagArrayRead, TagArrayWrite, DataArrayRead, DataArrayWrite} {
|
|
a_allocate;
|
|
w_writeCache;
|
|
l_loadDoneMiss;
|
|
pr_popResponseQueue;
|
|
}
|
|
|
|
transition(I, Bypass, I) {
|
|
rb_bypassDone;
|
|
pr_popResponseQueue;
|
|
}
|
|
|
|
transition(A, Bypass, I){
|
|
d_deallocateTBE;
|
|
wab_bypassDone;
|
|
pr_popResponseQueue;
|
|
}
|
|
|
|
transition(A, TCC_Ack, I) {TagArrayRead, DataArrayRead, DataArrayWrite} {
|
|
d_deallocateTBE;
|
|
a_allocate;
|
|
w_writeCache;
|
|
ad_atomicDone;
|
|
pr_popResponseQueue;
|
|
ic_invCache;
|
|
}
|
|
|
|
transition(V, TCC_Ack, V) {TagArrayRead, DataArrayRead, DataArrayWrite} {
|
|
w_writeCache;
|
|
l_loadDoneHit;
|
|
pr_popResponseQueue;
|
|
}
|
|
|
|
transition({I, V}, Repl, I) {TagArrayRead, TagArrayWrite} {
|
|
ic_invCache;
|
|
}
|
|
|
|
transition({A}, Repl) {TagArrayRead, TagArrayWrite} {
|
|
ic_invCache;
|
|
}
|
|
|
|
transition({V,I}, Flush, F) {TagArrayFlash} {
|
|
a_allocate;
|
|
sf_setFlush;
|
|
p_popMandatoryQueue;
|
|
}
|
|
|
|
transition(A, Flush) {
|
|
z_stall;
|
|
}
|
|
|
|
transition({I, V}, Evict, I) {TagArrayFlash} {
|
|
inv_invDone;
|
|
p_popMandatoryQueue;
|
|
ic_invCache;
|
|
}
|
|
|
|
transition(A, Evict) {TagArrayFlash} {
|
|
inv_invDone;
|
|
p_popMandatoryQueue;
|
|
}
|
|
|
|
// TCC_AckWB only snoops TBE
|
|
transition({V, I, A}, TCC_AckWB) {
|
|
wd_wtDone;
|
|
pr_popResponseQueue;
|
|
}
|
|
|
|
transition(F, TCC_AckWB, I) {
|
|
f_flushDone;
|
|
pr_popResponseQueue;
|
|
ic_invCache;
|
|
}
|
|
}
|