stdlib: Fix RISCVBoard when running O3 CPU with Ruby

The long/nightly tests were failing,
https://jenkins.gem5.org/job/nightly/47, due to a misconfiguration in
the RISCVBoard that caused a "fatal: Unable to find destination " error
when running the O3 CPU with a Ruby cache coherence protocol.

This patch resolves the issue by adding a "BadAddr" to handle bad
addresses occasionally produced by the O3 CPU.

Change-Id: I07fe06544e7588f45984032a022e73cd41d8a1e6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52963
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

src/python/gem5/components/boards/riscv_board.py

@@ -42,6 +42,7 @@ from ...utils.requires import requires
 import m5
 
 from m5.objects import (
+    BadAddr,
     Bridge,
     PMAChecker,
     RiscvLinux,
@@ -107,6 +108,8 @@ class RiscvBoard(AbstractBoard, KernelDiskWorkload):
 
         # Incoherent I/O bus
         self.iobus = IOXBar()
+        self.iobus.badaddr_responder = BadAddr()
+        self.iobus.default = self.iobus.badaddr_responder.pio
 
         # The virtio disk
         self.disk = RiscvMmioVirtIO(