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ARM: Implement the version of VMRS that writes to the APSR.

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This commit is contained in:
Gabe Black
2010-06-02 12:58:15 -05:00
parent 57c4d37c10
commit 2d08b8de91
3 changed files with 20 additions and 1 deletions
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12
src/arch/arm/isa/formats/fp.isa
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@@ -409,7 +409,17 @@ let {{
default:
return new Unknown(machInst);
}
return new Vmrs(machInst, rt, (IntRegIndex)specReg);
if (rt == 0xf) {
CPSR cpsrMask = 0;
cpsrMask.n = 1;
cpsrMask.z = 1;
cpsrMask.c = 1;
cpsrMask.v = 1;
return new VmrsApsr(machInst, INTREG_CONDCODES,
(IntRegIndex)specReg, (uint32_t)cpsrMask);
} else {
return new Vmrs(machInst, rt, (IntRegIndex)specReg);
}
}
} else {
uint32_t vd = (bits(machInst, 7) << 5) |

1
src/arch/arm/isa/includes.isa
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@@ -63,6 +63,7 @@ output header {{
output decoder {{
#include "arch/arm/faults.hh"
#include "arch/arm/intregs.hh"
#include "arch/arm/isa_traits.hh"
#include "arch/arm/utility.hh"
#include "base/cprintf.hh"

8
src/arch/arm/isa/insts/fp.isa
View File

@@ -205,6 +205,14 @@ let {{
decoder_output += VfpRegRegOpConstructor.subst(vmrsIop);
exec_output += PredOpExecute.subst(vmrsIop);
vmrsApsrCode = "Dest = (MiscOp1 & imm) | (Dest & ~imm);"
vmrsApsrIop = InstObjParams("vmrs", "VmrsApsr", "VfpRegRegImmOp",
{ "code": vmrsApsrCode,
"predicate_test": predicateTest }, [])
header_output += VfpRegRegImmOpDeclare.subst(vmrsApsrIop);
decoder_output += VfpRegRegImmOpConstructor.subst(vmrsApsrIop);
exec_output += PredOpExecute.subst(vmrsApsrIop);
vmovImmSCode = '''
FpDest.uw = bits(imm, 31, 0);
'''