ARM: Ignore reads and writes to DCIMVAC.

2010-06-02 12:58:15 -05:00
parent fd37095fa6
commit 57c4d37c10
1 changed files with 3 additions and 0 deletions
--- a/src/arch/arm/isa/formats/misc.isa
+++ b/src/arch/arm/isa/formats/misc.isa
@@ -107,6 +107,9 @@ let {{
          case MISCREG_DCCIMVAC:
            return new WarnUnimplemented(
                    isRead ? "mrc dccimvac" : "mcr dccimvac", machInst);
+          case MISCREG_DCIMVAC:
+            return new WarnUnimplemented(
+                    isRead ? "mrc dcimvac" : "mcr dcimvac", machInst);
          case MISCREG_DCCMVAC:
            return new WarnUnimplemented(
                    isRead ? "mrc dccmvac" : "mcr dccmvac", machInst);