misc: Merge branch v20.1.0.3 hotfix into develop

Change-Id: I12cca586627718bf41fe24f0fcd3f10c4fe48b2d

RELEASE-NOTES.md

@@ -1,3 +1,8 @@
+# Version 20.1.0.3
+
+**[HOTFIX]** A patch was apply to fix an [error where booting Linux stalled when using the ARM ISA](https://gem5.atlassian.net/browse/GEM5-901).
+This fix adds the parameter `have_vhe` to enable FEAT_VHE on demand, and is disabled by default to resolve this issue.
+
 # Version 20.1.0.2
 
 **[HOTFIX]** This hotfix release fixes known two bugs:

src/Doxyfile

@@ -31,7 +31,7 @@ PROJECT_NAME           = gem5
 # This could be handy for archiving the generated documentation or 
 # if some version control system is used.
 
-PROJECT_NUMBER         = DEVELOP-FOR-V20.2
+PROJECT_NUMBER         = v20.1.0.3
 
 # The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute) 
 # base path where the generated documentation will be put. 

src/arch/arm/ArmISA.py

@@ -1,4 +1,4 @@
-# Copyright (c) 2012-2013, 2015-2020 ARM Limited
+# Copyright (c) 2012-2013, 2015-2021 ARM Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -113,8 +113,8 @@ class ArmISA(BaseISA):
     # 4K | 64K | !16K | !BigEndEL0 | !SNSMem | !BigEnd | 8b ASID | 40b PA
     id_aa64mmfr0_el1 = Param.UInt64(0x0000000000f00002,
         "AArch64 Memory Model Feature Register 0")
-    # PAN | HPDS | VHE
-    id_aa64mmfr1_el1 = Param.UInt64(0x0000000000101100,
+    # PAN | HPDS | !VHE
+    id_aa64mmfr1_el1 = Param.UInt64(0x0000000000101000,
         "AArch64 Memory Model Feature Register 1")
     # |VARANGE
     id_aa64mmfr2_el1 = Param.UInt64(0x0000000000010000,

src/arch/arm/ArmSystem.py

@@ -1,4 +1,4 @@
-# Copyright (c) 2009, 2012-2013, 2015-2020 ARM Limited
+# Copyright (c) 2009, 2012-2013, 2015-2021 ARM Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -72,6 +72,8 @@ class ArmSystem(System):
         "SVE vector length in quadwords (128-bit)")
     have_lse = Param.Bool(True,
         "True if LSE is implemented (ARMv8.1)")
+    have_vhe = Param.Bool(False,
+        "True if FEAT_VHE (Virtualization Host Extensions) is implemented")
     have_pan = Param.Bool(True,
         "True if Priviledge Access Never is implemented (ARMv8.1)")
     have_secel2 = Param.Bool(True,

src/arch/arm/isa.cc

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010-2020 ARM Limited
+ * Copyright (c) 2010-2021 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -88,6 +88,7 @@ ISA::ISA(const Params &p) : BaseISA(p), system(NULL),
         haveLargeAsid64 = system->haveLargeAsid64();
         physAddrRange = system->physAddrRange();
         haveSVE = system->haveSVE();
+        haveVHE = system->haveVHE();
         havePAN = system->havePAN();
         haveSecEL2 = system->haveSecEL2();
         sveVL = system->sveVL();
@@ -100,6 +101,7 @@ ISA::ISA(const Params &p) : BaseISA(p), system(NULL),
         haveLargeAsid64 = false;
         physAddrRange = 32;  // dummy value
         haveSVE = true;
+        haveVHE = false;
         havePAN = false;
         haveSecEL2 = true;
         sveVL = p.sve_vl_se;
@@ -426,6 +428,10 @@ ISA::initID64(const ArmISAParams &p)
     miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits(
         miscRegs[MISCREG_ID_AA64ISAR0_EL1], 23, 20,
         haveLSE ? 0x2 : 0x0);
+    // VHE
+    miscRegs[MISCREG_ID_AA64MMFR1_EL1] = insertBits(
+        miscRegs[MISCREG_ID_AA64MMFR1_EL1], 11, 8,
+        haveVHE ? 0x1 : 0x0);
     // PAN
     miscRegs[MISCREG_ID_AA64MMFR1_EL1] = insertBits(
         miscRegs[MISCREG_ID_AA64MMFR1_EL1], 23, 20,

src/arch/arm/isa.hh

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010, 2012-2020 ARM Limited
+ * Copyright (c) 2010, 2012-2021 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -94,6 +94,7 @@ namespace ArmISA
         uint8_t physAddrRange;
         bool haveSVE;
         bool haveLSE;
+        bool haveVHE;
         bool havePAN;
         bool haveSecEL2;
         bool haveTME;

src/arch/arm/system.cc

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010, 2012-2013, 2015,2017-2020 ARM Limited
+ * Copyright (c) 2010, 2012-2013, 2015,2017-2021 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -70,6 +70,7 @@ ArmSystem::ArmSystem(const Params &p)
       _haveSVE(p.have_sve),
       _sveVL(p.sve_vl),
       _haveLSE(p.have_lse),
+      _haveVHE(p.have_vhe),
       _havePAN(p.have_pan),
       _haveSecEL2(p.have_secel2),
       semihosting(p.semihosting),

src/arch/arm/system.hh

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010, 2012-2013, 2015-2020 ARM Limited
+ * Copyright (c) 2010, 2012-2013, 2015-2021 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -130,6 +130,9 @@ class ArmSystem : public System
      */
     const bool _haveLSE;
 
+    /** True if FEAT_VHE (Virtualization Host Extensions) is implemented */
+    const bool _haveVHE;
+
     /** True if Priviledge Access Never is implemented */
     const unsigned _havePAN;
 
@@ -236,6 +239,9 @@ class ArmSystem : public System
     /** Returns true if LSE is implemented (ARMv8.1) */
     bool haveLSE() const { return _haveLSE; }
 
+    /** Returns true if Virtualization Host Extensions is implemented */
+    bool haveVHE() const { return _haveVHE; }
+
     /** Returns true if Priviledge Access Never is implemented */
     bool havePAN() const { return _havePAN; }
 

src/base/version.cc

@@ -29,4 +29,4 @@
 /**
  * @ingroup api_base_utils
  */
-const char *gem5Version = "[DEVELOP-FOR-V20.2]";
+const char *gem5Version = "20.1.0.3";