365 lines
12 KiB
C++
365 lines
12 KiB
C++
/*
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* Copyright (c) 2010, 2012-2013, 2015-2021 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2002-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __ARCH_ARM_SYSTEM_HH__
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#define __ARCH_ARM_SYSTEM_HH__
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#include <memory>
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#include <string>
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#include <vector>
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#include "kern/linux/events.hh"
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#include "params/ArmSystem.hh"
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#include "sim/full_system.hh"
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#include "sim/sim_object.hh"
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#include "sim/system.hh"
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class GenericTimer;
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class BaseGic;
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class FVPBasePwrCtrl;
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class ThreadContext;
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class ArmSystem : public System
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{
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protected:
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/**
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* True if this system implements the Security Extensions
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*/
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const bool _haveSecurity;
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/**
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* True if this system implements the Large Physical Address Extension
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*/
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const bool _haveLPAE;
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/**
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* True if this system implements the virtualization Extensions
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*/
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const bool _haveVirtualization;
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/**
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* True if this system implements the Crypto Extension
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*/
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const bool _haveCrypto;
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/**
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* Pointer to the Generic Timer wrapper.
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*/
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GenericTimer *_genericTimer;
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BaseGic *_gic;
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/**
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* Pointer to the Power Controller (if any)
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*/
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FVPBasePwrCtrl *_pwrCtrl;
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/**
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* Reset address (ARMv8)
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*/
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Addr _resetAddr;
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/**
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* True if the register width of the highest implemented exception level is
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* 64 bits (ARMv8)
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*/
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bool _highestELIs64;
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/**
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* Supported physical address range in bits if the highest implemented
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* exception level is 64 bits (ARMv8)
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*/
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const uint8_t _physAddrRange64;
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/**
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* True if ASID is 16 bits in AArch64 (ARMv8)
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*/
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const bool _haveLargeAsid64;
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/**
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* True if system implements the transactional memory extension (TME)
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*/
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const bool _haveTME;
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/**
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* True if SVE is implemented (ARMv8)
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*/
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const bool _haveSVE;
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/** SVE vector length at reset, in quadwords */
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const unsigned _sveVL;
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/**
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* True if LSE is implemented (ARMv8.1)
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*/
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const bool _haveLSE;
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/** True if FEAT_VHE (Virtualization Host Extensions) is implemented */
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const bool _haveVHE;
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/** True if Priviledge Access Never is implemented */
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const unsigned _havePAN;
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/** True if Secure EL2 is implemented */
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const unsigned _haveSecEL2;
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/**
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* True if the Semihosting interface is enabled.
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*/
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ArmSemihosting *const semihosting;
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public:
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static constexpr Addr PageBytes = ArmISA::PageBytes;
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static constexpr Addr PageShift = ArmISA::PageShift;
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typedef ArmSystemParams Params;
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const Params &
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params() const
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{
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return dynamic_cast<const Params &>(_params);
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}
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ArmSystem(const Params &p);
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/** true if this a multiprocessor system */
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bool multiProc;
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/** Returns true if this system implements the Security Extensions */
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bool haveSecurity() const { return _haveSecurity; }
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/** Returns true if this system implements the Large Physical Address
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* Extension */
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bool haveLPAE() const { return _haveLPAE; }
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/** Returns true if this system implements the virtualization
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* Extensions
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*/
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bool haveVirtualization() const { return _haveVirtualization; }
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/** Returns true if this system implements the Crypto
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* Extension
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*/
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bool haveCrypto() const { return _haveCrypto; }
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/** Sets the pointer to the Generic Timer. */
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void
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setGenericTimer(GenericTimer *generic_timer)
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{
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_genericTimer = generic_timer;
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}
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/** Sets the pointer to the GIC. */
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void setGIC(BaseGic *gic) { _gic = gic; }
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/** Sets the pointer to the Power Controller */
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void setPowerController(FVPBasePwrCtrl *pwr_ctrl)
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{
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_pwrCtrl = pwr_ctrl;
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}
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/** Get a pointer to the system's generic timer model */
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GenericTimer *getGenericTimer() const { return _genericTimer; }
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/** Get a pointer to the system's GIC */
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BaseGic *getGIC() const { return _gic; }
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/** Get a pointer to the system's power controller */
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FVPBasePwrCtrl *getPowerController() const { return _pwrCtrl; }
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/** Returns true if the register width of the highest implemented exception
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* level is 64 bits (ARMv8) */
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bool highestELIs64() const { return _highestELIs64; }
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/** Returns the highest implemented exception level */
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ArmISA::ExceptionLevel
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highestEL() const
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{
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if (_haveSecurity)
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return ArmISA::EL3;
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if (_haveVirtualization)
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return ArmISA::EL2;
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return ArmISA::EL1;
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}
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/** Returns the reset address if the highest implemented exception level is
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* 64 bits (ARMv8) */
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Addr resetAddr() const { return _resetAddr; }
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void setResetAddr(Addr addr) { _resetAddr = addr; }
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/** Returns true if ASID is 16 bits in AArch64 (ARMv8) */
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bool haveLargeAsid64() const { return _haveLargeAsid64; }
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/** Returns true if this system implements the transactional
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* memory extension (ARMv9)
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*/
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bool haveTME() const { return _haveTME; }
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/** Returns true if SVE is implemented (ARMv8) */
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bool haveSVE() const { return _haveSVE; }
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/** Returns the SVE vector length at reset, in quadwords */
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unsigned sveVL() const { return _sveVL; }
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/** Returns true if LSE is implemented (ARMv8.1) */
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bool haveLSE() const { return _haveLSE; }
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/** Returns true if Virtualization Host Extensions is implemented */
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bool haveVHE() const { return _haveVHE; }
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/** Returns true if Priviledge Access Never is implemented */
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bool havePAN() const { return _havePAN; }
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/** Returns true if Priviledge Access Never is implemented */
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bool haveSecEL2() const { return _haveSecEL2; }
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/** Returns the supported physical address range in bits if the highest
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* implemented exception level is 64 bits (ARMv8) */
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uint8_t physAddrRange64() const { return _physAddrRange64; }
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/** Returns the supported physical address range in bits */
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uint8_t
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physAddrRange() const
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{
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if (_highestELIs64)
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return _physAddrRange64;
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if (_haveLPAE)
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return 40;
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return 32;
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}
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/** Returns the physical address mask */
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Addr physAddrMask() const { return mask(physAddrRange()); }
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/** Is Arm Semihosting support enabled? */
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bool haveSemihosting() const { return semihosting != nullptr; }
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/**
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* Returns a valid ArmSystem pointer if using ARM ISA, it fails
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* otherwise.
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*/
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static ArmSystem*
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getArmSystem(ThreadContext *tc)
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{
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assert(FullSystem);
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return static_cast<ArmSystem *>(tc->getSystemPtr());
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}
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/** Returns true if the system of a specific thread context implements the
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* Security Extensions
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*/
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static bool haveSecurity(ThreadContext *tc);
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/** Returns true if the system of a specific thread context implements the
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* virtualization Extensions
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*/
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static bool haveVirtualization(ThreadContext *tc);
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/** Returns true if the system of a specific thread context implements the
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* Large Physical Address Extension
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*/
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static bool haveLPAE(ThreadContext *tc);
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/** Returns true if the register width of the highest implemented exception
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* level for the system of a specific thread context is 64 bits (ARMv8)
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*/
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static bool highestELIs64(ThreadContext *tc);
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/** Returns the highest implemented exception level for the system of a
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* specific thread context
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*/
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static ArmISA::ExceptionLevel highestEL(ThreadContext *tc);
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/** Return true if the system implements a specific exception level */
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static bool haveEL(ThreadContext *tc, ArmISA::ExceptionLevel el);
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/** Returns true if the system of a specific thread context implements the
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* transactional memory extension (TME)
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*/
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static bool haveTME(ThreadContext *tc);
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/** Returns the reset address if the highest implemented exception level
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* for the system of a specific thread context is 64 bits (ARMv8)
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*/
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static Addr resetAddr(ThreadContext *tc);
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/** Returns the supported physical address range in bits for the system of a
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* specific thread context
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*/
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static uint8_t physAddrRange(ThreadContext *tc);
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/** Returns the physical address mask for the system of a specific thread
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* context
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*/
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static Addr physAddrMask(ThreadContext *tc);
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/** Returns true if ASID is 16 bits for the system of a specific thread
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* context while in AArch64 (ARMv8) */
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static bool haveLargeAsid64(ThreadContext *tc);
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/** Is Arm Semihosting support enabled? */
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static bool haveSemihosting(ThreadContext *tc);
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/** Make a Semihosting call from aarch64 */
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static bool callSemihosting64(ThreadContext *tc, bool gem5_ops=false);
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/** Make a Semihosting call from aarch32 */
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static bool callSemihosting32(ThreadContext *tc, bool gem5_ops=false);
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/** Make a Semihosting call from either aarch64 or aarch32 */
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static bool callSemihosting(ThreadContext *tc, bool gem5_ops=false);
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/** Make a call to notify the power controller of STANDBYWFI assertion */
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static void callSetStandByWfi(ThreadContext *tc);
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/** Make a call to notify the power controller of STANDBYWFI deassertion */
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static void callClearStandByWfi(ThreadContext *tc);
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/**
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* Notify the power controller of WAKEREQUEST assertion. Returns true
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* if WAKEREQUEST is enabled as a power-on mechanism, and the core is now
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* powered, false otherwise
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*/
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static bool callSetWakeRequest(ThreadContext *tc);
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/** Notify the power controller of WAKEREQUEST deassertion */
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static void callClearWakeRequest(ThreadContext *tc);
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};
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#endif
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