derek/gem5
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

arch-arm: Remove legacy ThumbEE references

Browse Source 
ThumbEE had already been removed but there were still some
references to it dangling around. We were also signaling
ThumbEE as being available through HWCAPS in SE which
was not correct. This patch is fixing it

Change-Id: I8b196f5bd27822cd4dd8b3ab3ad9f12a6f54b047
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
This commit is contained in:
Giacomo Travaglini
2023-09-27 09:34:19 +01:00
parent a33f3d3967
commit 1c45cdcc41
5 changed files with 4 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/arch/arm/fastmodel/CortexA76/thread_context.cc
View File

@@ -228,7 +228,7 @@ Iris::ThreadContext::IdxNameMap CortexA76TC::miscRegIdxNameMap({
// ArmISA::MISCREG_SCTLR_RST?
{ ArmISA::MISCREG_SEV_MAILBOX, "SEV_STATE" },
// AArch32 CP14 registers (debug/trace/ThumbEE control)
// AArch32 CP14 registers (debug/trace control)
// ArmISA::MISCREG_DBGDIDR?
// ArmISA::MISCREG_DBGDSCRint?
// ArmISA::MISCREG_DBGDCCINT?

2
src/arch/arm/fastmodel/CortexR52/thread_context.cc
View File

@@ -188,7 +188,7 @@ Iris::ThreadContext::IdxNameMap CortexR52TC::miscRegIdxNameMap({
// ArmISA::MISCREG_SCTLR_RST?
// ArmISA::MISCREG_SEV_MAILBOX?
// AArch32 CP14 registers (debug/trace/ThumbEE control)
// AArch32 CP14 registers (debug/trace control)
// ArmISA::MISCREG_DBGDIDR?
// ArmISA::MISCREG_DBGDSCRint?
// ArmISA::MISCREG_DBGDCCINT?

2
src/arch/arm/process.cc
View File

@@ -169,7 +169,7 @@ ArmProcess32::armHwcapImpl() const
};
return Arm_Swp | Arm_Half | Arm_Thumb | Arm_FastMult |
Arm_Vfp | Arm_Edsp | Arm_ThumbEE | Arm_Neon |
Arm_Vfp | Arm_Edsp | Arm_Neon |
Arm_Vfpv3 | Arm_Vfpv3d16;
}

2
src/arch/arm/regs/misc.hh
View File

@@ -96,7 +96,7 @@ namespace ArmISA
MISCREG_SEV_MAILBOX,
MISCREG_TLBINEEDSYNC,
// AArch32 CP14 registers (debug/trace/ThumbEE control)
// AArch32 CP14 registers (debug/trace control)
MISCREG_DBGDIDR,
MISCREG_DBGDSCRint,
MISCREG_DBGDCCINT,

2
src/arch/arm/regs/misc_types.hh
View File

@@ -457,8 +457,6 @@ namespace ArmISA
Bitfield<7> itd; // IT disable
// (ARMv8 AArch32 and AArch64 SCTLR_EL1 only)
Bitfield<6, 3> rao4; // Read as one
Bitfield<6> thee; // ThumbEE enable
// (ARMv8 AArch32 and AArch64 SCTLR_EL1 only)
Bitfield<5> cp15ben; // CP15 barrier enable
// (AArch32 and AArch64 SCTLR_EL1 only)
Bitfield<4> sa0; // Stack Alignment Check Enable for EL0