arch-arm: Initialize some cases of destReg

Some compilers complained that this variable may be uninitialized. This
change initializes it to 0.

Change-Id: I201d75ba05ce49d13bbaf4d67e1c728ef704fdf0
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34335
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: mike upton <michaelupton@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Jason Lowe-Power
2020-09-10 14:58:15 -07:00
committed by Bobby R. Bruce
parent 69e3e508c7
commit 1c3e411834
2 changed files with 6 additions and 6 deletions

View File

@@ -1452,7 +1452,7 @@ let {{
rCount = 2
eWalkCode = simdEnabledCheckCode + '''
RegVect srcReg1, srcReg2;
BigRegVect destReg;
BigRegVect destReg = {0};
'''
for reg in range(rCount):
eWalkCode += '''
@@ -1654,7 +1654,7 @@ let {{
global header_output, exec_output
eWalkCode = simdEnabledCheckCode + '''
RegVect srcReg1;
BigRegVect destReg;
BigRegVect destReg = {0};
'''
for reg in range(2):
eWalkCode += '''
@@ -1884,7 +1884,7 @@ let {{
global header_output, exec_output
eWalkCode = simdEnabledCheckCode + '''
RegVect srcRegs;
BigRegVect destReg;
BigRegVect destReg = {0};
'''
for reg in range(rCount):
eWalkCode += '''
@@ -2010,7 +2010,7 @@ let {{
global header_output, exec_output
eWalkCode = simdEnabledCheckCode + '''
RegVect srcReg1;
BigRegVect destReg;
BigRegVect destReg = {0};
'''
for reg in range(2):
eWalkCode += '''

View File

@@ -351,7 +351,7 @@ let {{
global header_output, exec_output
eWalkCode = simd64EnabledCheckCode + '''
RegVect srcReg1;
BigRegVect destReg;
BigRegVect destReg = {0};
'''
destReg = 0 if not hi else 2
for reg in range(2):
@@ -632,7 +632,7 @@ let {{
global header_output, exec_output
eWalkCode = simd64EnabledCheckCode + '''
RegVect srcRegs;
BigRegVect destReg;
BigRegVect destReg = {0};
'''
for reg in range(rCount):
eWalkCode += '''