diff --git a/src/arch/arm/isa/insts/neon.isa b/src/arch/arm/isa/insts/neon.isa index 1dfefe7c30..c8f8fcd849 100644 --- a/src/arch/arm/isa/insts/neon.isa +++ b/src/arch/arm/isa/insts/neon.isa @@ -1452,7 +1452,7 @@ let {{ rCount = 2 eWalkCode = simdEnabledCheckCode + ''' RegVect srcReg1, srcReg2; - BigRegVect destReg; + BigRegVect destReg = {0}; ''' for reg in range(rCount): eWalkCode += ''' @@ -1654,7 +1654,7 @@ let {{ global header_output, exec_output eWalkCode = simdEnabledCheckCode + ''' RegVect srcReg1; - BigRegVect destReg; + BigRegVect destReg = {0}; ''' for reg in range(2): eWalkCode += ''' @@ -1884,7 +1884,7 @@ let {{ global header_output, exec_output eWalkCode = simdEnabledCheckCode + ''' RegVect srcRegs; - BigRegVect destReg; + BigRegVect destReg = {0}; ''' for reg in range(rCount): eWalkCode += ''' @@ -2010,7 +2010,7 @@ let {{ global header_output, exec_output eWalkCode = simdEnabledCheckCode + ''' RegVect srcReg1; - BigRegVect destReg; + BigRegVect destReg = {0}; ''' for reg in range(2): eWalkCode += ''' diff --git a/src/arch/arm/isa/insts/neon64.isa b/src/arch/arm/isa/insts/neon64.isa index b9729a160f..702c128ccf 100644 --- a/src/arch/arm/isa/insts/neon64.isa +++ b/src/arch/arm/isa/insts/neon64.isa @@ -351,7 +351,7 @@ let {{ global header_output, exec_output eWalkCode = simd64EnabledCheckCode + ''' RegVect srcReg1; - BigRegVect destReg; + BigRegVect destReg = {0}; ''' destReg = 0 if not hi else 2 for reg in range(2): @@ -632,7 +632,7 @@ let {{ global header_output, exec_output eWalkCode = simd64EnabledCheckCode + ''' RegVect srcRegs; - BigRegVect destReg; + BigRegVect destReg = {0}; ''' for reg in range(rCount): eWalkCode += '''