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arm: Get rid of some unused instruction templates.

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These were defined but not used.

Change-Id: Ib81e86c8b8640e2f47ff7ad84d287367462e04a5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36975
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
2020-11-03 18:21:27 -08:00
parent 84e18a7a47
commit 1a2b677728
2 changed files with 0 additions and 95 deletions
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68
src/arch/arm/isa/templates/branch.isa
View File

@@ -35,34 +35,6 @@
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
def template BranchImmDeclare {{
class %(class_name)s : public %(base_class)s
{
public:
// Constructor
%(class_name)s(ExtMachInst machInst, int32_t _imm);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
};
}};
def template BranchImmConstructor {{
%(class_name)s::%(class_name)s(ExtMachInst machInst,
int32_t _imm)
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm)
{
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
_srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
}
flags[IsCondControl] = true;
} else {
flags[IsUncondControl] = true;
}
}
}};
def template BranchImmCondDeclare {{
class %(class_name)s : public %(base_class)s
{
@@ -98,35 +70,6 @@ def template BranchImmCondConstructor {{
}
}};
def template BranchRegDeclare {{
class %(class_name)s : public %(base_class)s
{
public:
// Constructor
%(class_name)s(ExtMachInst machInst, IntRegIndex _op1);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
};
}};
def template BranchRegConstructor {{
%(class_name)s::%(class_name)s(ExtMachInst machInst,
IntRegIndex _op1)
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1)
{
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
_srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
}
flags[IsCondControl] = true;
} else {
flags[IsUncondControl] = true;
}
if (%(is_ras_pop)s)
flags[IsReturn] = true;
}
}};
def template BranchRegCondDeclare {{
class %(class_name)s : public %(base_class)s
{
@@ -159,17 +102,6 @@ def template BranchRegCondConstructor {{
}
}};
def template BranchRegRegDeclare {{
class %(class_name)s : public %(base_class)s
{
public:
// Constructor
%(class_name)s(ExtMachInst machInst,
IntRegIndex _op1, IntRegIndex _op2);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
};
}};
def template BranchTableDeclare {{
class %(class_name)s : public %(base_class)s
{

27
src/arch/arm/isa/templates/macromem.isa
View File

@@ -183,33 +183,6 @@ def template MicroSetPCCPSRConstructor {{
// Integer = Integer op Integer microops
//
def template MicroIntDeclare {{
class %(class_name)s : public %(base_class)s
{
public:
%(class_name)s(ExtMachInst machInst,
RegIndex _ura, RegIndex _urb, RegIndex _urc);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
};
}};
def template MicroIntConstructor {{
%(class_name)s::%(class_name)s(ExtMachInst machInst,
RegIndex _ura,
RegIndex _urb,
RegIndex _urc)
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_ura, _urb, _urc)
{
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
_srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
}
}
}
}};
def template MicroNeonMemExecDeclare {{
template
Fault %(class_name)s<%(targs)s>::execute(