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mips: Fix the build after the MMU changes.

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Change-Id: I2bd1a6a8607fe1da056182ca840036db35b53c36
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36995
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
2020-11-03 20:54:01 -08:00
committed by mike upton
parent 3d20460c22
commit 84e18a7a47
2 changed files with 5 additions and 4 deletions
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8
src/arch/mips/isa/decoder.isa
View File

@@ -738,7 +738,7 @@ decode OPCODE_HI default Unknown::unknown() {
0x01: tlbr({{
MipsISA::PTE *PTEntry =
dynamic_cast<MipsISA::TLB *>(
xc->tcBase()->getITBPtr())->
xc->tcBase()->getMMUPtr()->itb)->
getEntry(Index & 0x7FFFFFFF);
if (PTEntry == NULL) {
fatal("Invalid PTE Entry received on "
@@ -819,7 +819,7 @@ decode OPCODE_HI default Unknown::unknown() {
(1 << newEntry.AddrShiftAmount) - 1;
auto ptr = dynamic_cast<MipsISA::TLB *>(
xc->tcBase()->getITBPtr());
xc->tcBase()->getMMUPtr()->itb);
Config3Reg config3 = Config3;
PageGrainReg pageGrain = PageGrain;
int SP = 0;
@@ -885,7 +885,7 @@ decode OPCODE_HI default Unknown::unknown() {
(1 << newEntry.AddrShiftAmount) - 1;
auto ptr = dynamic_cast<MipsISA::TLB *>(
xc->tcBase()->getITBPtr());
xc->tcBase()->getMMUPtr()->itb);
Config3Reg config3 = Config3;
PageGrainReg pageGrain = PageGrain;
int SP = 0;
@@ -909,7 +909,7 @@ decode OPCODE_HI default Unknown::unknown() {
vpn = ((EntryHi >> 11) & 0xFFFFFFFC);
}
tlbIndex = dynamic_cast<MipsISA::TLB *>(
xc->tcBase()->getITBPtr())->
xc->tcBase()->getMMUPtr()->itb)->
probeEntry(vpn, entryHi.asid);
// Check TLB for entry matching EntryHi
if (tlbIndex != -1) {

1
src/arch/mips/isa/includes.isa
View File

@@ -76,6 +76,7 @@ output exec {{
#include "arch/mips/dt_constants.hh"
#include "arch/mips/faults.hh"
#include "arch/mips/isa_traits.hh"
#include "arch/mips/mmu.hh"
#include "arch/mips/mt.hh"
#include "arch/mips/mt_constants.hh"
#include "arch/mips/pagetable.hh"