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cpu: Implement (get|set)Reg(Flat|) for the checker CPU.

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These are very simple, since they just delegate to other TCs.

Change-Id: I08fd8de09c90c74548987d537e282edc297ac4e8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49111
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
This commit is contained in:
Gabe Black
2021-08-06 04:41:16 -07:00
parent 5c9b4c096f
commit 17c7f33fdb
1 changed files with 64 additions and 0 deletions
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64
src/cpu/checker/thread_context.hh
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@@ -226,6 +226,38 @@ class CheckerThreadContext : public ThreadContext
//
// New accessors for new decoder.
//
RegVal
getReg(const RegId &reg) const override
{
return actualTC->getReg(reg);
}
void
getReg(const RegId &reg, void *val) const override
{
actualTC->getReg(reg, val);
}
void *
getWritableReg(const RegId &reg) override
{
return actualTC->getWritableReg(reg);
}
void
setReg(const RegId &reg, RegVal val) override
{
actualTC->setReg(reg, val);
checkerTC->setReg(reg, val);
}
void
setReg(const RegId &reg, const void *val) override
{
actualTC->setReg(reg, val);
checkerTC->setReg(reg, val);
}
RegVal
readIntReg(RegIndex reg_idx) const override
{
@@ -388,6 +420,38 @@ class CheckerThreadContext : public ThreadContext
actualTC->setStCondFailures(sc_failures);
}
RegVal
getRegFlat(const RegId &reg) const override
{
return actualTC->getRegFlat(reg);
}
void
getRegFlat(const RegId &reg, void *val) const override
{
actualTC->getRegFlat(reg, val);
}
void *
getWritableRegFlat(const RegId &reg) override
{
return actualTC->getWritableRegFlat(reg);
}
void
setRegFlat(const RegId &reg, RegVal val) override
{
actualTC->setRegFlat(reg, val);
checkerTC->setRegFlat(reg, val);
}
void
setRegFlat(const RegId &reg, const void *val) override
{
actualTC->setRegFlat(reg, val);
checkerTC->setRegFlat(reg, val);
}
RegVal
readIntRegFlat(RegIndex idx) const override
{