diff --git a/src/cpu/checker/thread_context.hh b/src/cpu/checker/thread_context.hh
index d97e7a03c6..f8c3ce7a65 100644
--- a/src/cpu/checker/thread_context.hh
+++ b/src/cpu/checker/thread_context.hh
@@ -226,6 +226,38 @@ class CheckerThreadContext : public ThreadContext
     //
     // New accessors for new decoder.
     //
+    RegVal
+    getReg(const RegId &reg) const override
+    {
+        return actualTC->getReg(reg);
+    }
+
+    void
+    getReg(const RegId &reg, void *val) const override
+    {
+        actualTC->getReg(reg, val);
+    }
+
+    void *
+    getWritableReg(const RegId &reg) override
+    {
+        return actualTC->getWritableReg(reg);
+    }
+
+    void
+    setReg(const RegId &reg, RegVal val) override
+    {
+        actualTC->setReg(reg, val);
+        checkerTC->setReg(reg, val);
+    }
+
+    void
+    setReg(const RegId &reg, const void *val) override
+    {
+        actualTC->setReg(reg, val);
+        checkerTC->setReg(reg, val);
+    }
+
     RegVal
     readIntReg(RegIndex reg_idx) const override
     {
@@ -388,6 +420,38 @@ class CheckerThreadContext : public ThreadContext
         actualTC->setStCondFailures(sc_failures);
     }
 
+    RegVal
+    getRegFlat(const RegId &reg) const override
+    {
+        return actualTC->getRegFlat(reg);
+    }
+
+    void
+    getRegFlat(const RegId &reg, void *val) const override
+    {
+        actualTC->getRegFlat(reg, val);
+    }
+
+    void *
+    getWritableRegFlat(const RegId &reg) override
+    {
+        return actualTC->getWritableRegFlat(reg);
+    }
+
+    void
+    setRegFlat(const RegId &reg, RegVal val) override
+    {
+        actualTC->setRegFlat(reg, val);
+        checkerTC->setRegFlat(reg, val);
+    }
+
+    void
+    setRegFlat(const RegId &reg, const void *val) override
+    {
+        actualTC->setRegFlat(reg, val);
+        checkerTC->setRegFlat(reg, val);
+    }
+
     RegVal
     readIntRegFlat(RegIndex idx) const override
     {