arch-riscv: Make c.flwsp destination register more maintainable (#1006)

RISC-V C.FLWSP format:


![image](https://github.com/gem5/gem5/assets/32214817/f4c8d114-cd6b-4946-afff-fa752b31e337)
The name FC1 and FD share the same bits, change to FC1 to make it better


ee6f1377d7/src/arch/riscv/isa/bitfields.isa (L110)


ee6f1377d7/src/arch/riscv/isa/operands.isa (L84)


ee6f1377d7/src/arch/riscv/isa/bitfields.isa (L85)


ee6f1377d7/src/arch/riscv/isa/operands.isa (L76)

src/arch/riscv/isa/decoder.isa

@@ -427,7 +427,7 @@ decode QUADRANT default Unknown::unknown() {
 
                     freg_t fd;
                     fd = freg(f32(Mem_uw));
-                    Fd_bits = fd.v;
+                    Fc1_bits = fd.v;
                 }}, {{
                     EA = (uint32_t)(sp_uw + offset);
                 }});