From 116c483a42d6b5681614198c500261ed2e429528 Mon Sep 17 00:00:00 2001 From: Yu-Cheng Chang Date: Wed, 10 Apr 2024 23:11:51 +0800 Subject: [PATCH] arch-riscv: Make c.flwsp destination register more maintainable (#1006) RISC-V C.FLWSP format: ![image](https://github.com/gem5/gem5/assets/32214817/f4c8d114-cd6b-4946-afff-fa752b31e337) The name FC1 and FD share the same bits, change to FC1 to make it better https://github.com/gem5/gem5/blob/ee6f1377d7c54422137dfa47cd4d73407814867d/src/arch/riscv/isa/bitfields.isa#L110 https://github.com/gem5/gem5/blob/ee6f1377d7c54422137dfa47cd4d73407814867d/src/arch/riscv/isa/operands.isa#L84 https://github.com/gem5/gem5/blob/ee6f1377d7c54422137dfa47cd4d73407814867d/src/arch/riscv/isa/bitfields.isa#L85 https://github.com/gem5/gem5/blob/ee6f1377d7c54422137dfa47cd4d73407814867d/src/arch/riscv/isa/operands.isa#L76 --- src/arch/riscv/isa/decoder.isa | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa index 30a46a5fa7..1d2b42b084 100644 --- a/src/arch/riscv/isa/decoder.isa +++ b/src/arch/riscv/isa/decoder.isa @@ -427,7 +427,7 @@ decode QUADRANT default Unknown::unknown() { freg_t fd; fd = freg(f32(Mem_uw)); - Fd_bits = fd.v; + Fc1_bits = fd.v; }}, {{ EA = (uint32_t)(sp_uw + offset); }});