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arch-riscv: Revamp int regs.

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Change-Id: Ie4773178843757acede4fe9e77ca327f7b024270
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49772
Reviewed-by: Boris Shingarov <shingarov@labware.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
This commit is contained in:
Gabe Black
2021-08-28 23:45:12 -07:00
parent 6a73a3a2d0
commit 0fa9bc0780
11 changed files with 93 additions and 33 deletions
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2
src/arch/riscv/linux/fs_workload.cc
View File

@@ -63,7 +63,7 @@ FsLinux::initState()
delete dtb_file;
for (auto *tc: system->threads) {
tc->setIntReg(11, params().dtb_addr);
tc->setReg(int_reg::A1, params().dtb_addr);
}
} else {
warn("No DTB file specified\n");

6
src/arch/riscv/linux/linux.hh
View File

@@ -203,9 +203,9 @@ class RiscvLinux64 : public RiscvLinux, public OpenFlagTable<RiscvLinux64>
{
ctc->getIsaPtr()->copyRegsFrom(ptc);
if (flags & TGT_CLONE_SETTLS)
ctc->setIntReg(RiscvISA::ThreadPointerReg, tls);
ctc->setReg(RiscvISA::ThreadPointerReg, tls);
if (stack)
ctc->setIntReg(RiscvISA::StackPointerReg, stack);
ctc->setReg(RiscvISA::StackPointerReg, stack);
}
};
@@ -372,7 +372,7 @@ class RiscvLinux32 : public RiscvLinux, public OpenFlagTable<RiscvLinux32>
{
ctc->getIsaPtr()->copyRegsFrom(ptc);
if (stack)
ctc->setIntReg(RiscvISA::StackPointerReg, stack);
ctc->setReg(RiscvISA::StackPointerReg, stack);
}
};

2
src/arch/riscv/linux/se_workload.cc
View File

@@ -86,7 +86,7 @@ EmuLinux::syscall(ThreadContext *tc)
// This will move into the base SEWorkload function at some point.
process->Process::syscall(tc);
RegVal num = tc->readIntReg(RiscvISA::SyscallNumReg);
RegVal num = tc->getReg(RiscvISA::SyscallNumReg);
if (dynamic_cast<RiscvProcess64 *>(process))
syscallDescs64.get(num)->doSyscall(tc);
else