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arch-arm: Declare support for Armv8.2-F64MM.

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Sets the appropriate bit in the ID_AA64ZFR0_EL1 sysreg that declares
support for ARMv8.2-F64MM.

This indicates that all pre-requisites for Armv8.2 SVE FP64
double-precision floating-point matrix multiplication instructions
have been met.

FMMLA, and LD1RO* instructions have been implemented, as well as the
128-bit element variants of TRN1, TRN2, UZP1, UZP2, ZIP1, and ZIP2.

For more information please refer to the "ARM Architecture Reference
Manual Supplement - The Scalable Vector Extension (SVE), for ARMv8-A"
(https://developer.arm.com/architectures/cpu-architecture/a-profile/
docs/arm-architecture-reference-manual-supplement-armv8-a)

Additional Contributors: Giacomo Travaglini

Change-Id: Idac3a3ca590e6eb2beb217a40a8c10af1e917440
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70729
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
This commit is contained in:
Richard Cooper
2020-10-08 19:35:47 +01:00
committed by Bobby Bruce
parent 8bf89d6967
commit 0f857873f9
4 changed files with 6 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
src/arch/arm/ArmISA.py
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@@ -54,6 +54,7 @@ class ArmDefaultSERelease(ArmRelease):
"FEAT_RDM",
# Armv8.2
"FEAT_F32MM",
"FEAT_F64MM",
"FEAT_SVE",
# Armv8.3
"FEAT_FCMA",

3
src/arch/arm/ArmSystem.py
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@@ -79,6 +79,7 @@ class ArmExtension(ScopedEnum):
"FEAT_LVA", # Optional in Armv8.2
"FEAT_LPA", # Optional in Armv8.2
"FEAT_F32MM", # Optional in Armv8.2
"FEAT_F64MM", # Optional in Armv8.2
# Armv8.3
"FEAT_FCMA",
"FEAT_JSCVT",
@@ -165,6 +166,7 @@ class ArmDefaultRelease(Armv8):
"FEAT_LPA",
"FEAT_SVE",
"FEAT_F32MM",
"FEAT_F64MM",
# Armv8.3
"FEAT_FCMA",
"FEAT_JSCVT",
@@ -199,6 +201,7 @@ class Armv82(Armv81):
"FEAT_LPA",
"FEAT_SVE",
"FEAT_F32MM",
"FEAT_F64MM",
]

1
src/arch/arm/process.cc
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@@ -322,6 +322,7 @@ ArmProcess64::armHwcapImpl2() const
const AA64ZFR0 zf_r0 = tc->readMiscReg(MISCREG_ID_AA64ZFR0_EL1);
hwcap |= (zf_r0.f32mm >= 1) ? Arm_Svef32mm : Arm_None;
hwcap |= (zf_r0.f64mm >= 1) ? Arm_Svef64mm : Arm_None;
return hwcap;
}

1
src/arch/arm/regs/misc.cc
View File

@@ -5406,6 +5406,7 @@ ISA::initializeMiscRegMetadata()
.reset([this](){
AA64ZFR0 zfr0_el1 = 0;
zfr0_el1.f32mm = release->has(ArmExtension::FEAT_F32MM) ? 1 : 0;
zfr0_el1.f64mm = release->has(ArmExtension::FEAT_F64MM) ? 1 : 0;
return zfr0_el1;
}())
.faultRead(EL0, faultIdst)