diff --git a/src/arch/arm/ArmISA.py b/src/arch/arm/ArmISA.py index 31ecbcbd15..fbd93b6bf6 100644 --- a/src/arch/arm/ArmISA.py +++ b/src/arch/arm/ArmISA.py @@ -54,6 +54,7 @@ class ArmDefaultSERelease(ArmRelease): "FEAT_RDM", # Armv8.2 "FEAT_F32MM", + "FEAT_F64MM", "FEAT_SVE", # Armv8.3 "FEAT_FCMA", diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py index 5a7ae799b7..49dab3e0e2 100644 --- a/src/arch/arm/ArmSystem.py +++ b/src/arch/arm/ArmSystem.py @@ -79,6 +79,7 @@ class ArmExtension(ScopedEnum): "FEAT_LVA", # Optional in Armv8.2 "FEAT_LPA", # Optional in Armv8.2 "FEAT_F32MM", # Optional in Armv8.2 + "FEAT_F64MM", # Optional in Armv8.2 # Armv8.3 "FEAT_FCMA", "FEAT_JSCVT", @@ -165,6 +166,7 @@ class ArmDefaultRelease(Armv8): "FEAT_LPA", "FEAT_SVE", "FEAT_F32MM", + "FEAT_F64MM", # Armv8.3 "FEAT_FCMA", "FEAT_JSCVT", @@ -199,6 +201,7 @@ class Armv82(Armv81): "FEAT_LPA", "FEAT_SVE", "FEAT_F32MM", + "FEAT_F64MM", ] diff --git a/src/arch/arm/process.cc b/src/arch/arm/process.cc index 24e1250da9..be8dfff330 100644 --- a/src/arch/arm/process.cc +++ b/src/arch/arm/process.cc @@ -322,6 +322,7 @@ ArmProcess64::armHwcapImpl2() const const AA64ZFR0 zf_r0 = tc->readMiscReg(MISCREG_ID_AA64ZFR0_EL1); hwcap |= (zf_r0.f32mm >= 1) ? Arm_Svef32mm : Arm_None; + hwcap |= (zf_r0.f64mm >= 1) ? Arm_Svef64mm : Arm_None; return hwcap; } diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc index 8925bc00d6..7e53e0dc24 100644 --- a/src/arch/arm/regs/misc.cc +++ b/src/arch/arm/regs/misc.cc @@ -5406,6 +5406,7 @@ ISA::initializeMiscRegMetadata() .reset([this](){ AA64ZFR0 zfr0_el1 = 0; zfr0_el1.f32mm = release->has(ArmExtension::FEAT_F32MM) ? 1 : 0; + zfr0_el1.f64mm = release->has(ArmExtension::FEAT_F64MM) ? 1 : 0; return zfr0_el1; }()) .faultRead(EL0, faultIdst)