arm: "Correct" the spelling of flavor.

In US English, flavor is spelled flavor, not flavour. The choice of
US spelling is arbitrary but consistent with gem5's history and the
rest of the code base.

Also fix a couple small style issues.

Change-Id: I307f8458fec5918a6fc34f938a4c12955d4d0565
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25010
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

src/arch/arm/ArmISA.py

@@ -44,8 +44,8 @@ from m5.objects.ArmSystem import SveVectorLength
 from m5.objects.BaseISA import BaseISA
 from m5.objects.ISACommon import VecRegRenameMode
 
-# Enum for DecoderFlavour
-class DecoderFlavour(Enum): vals = ['Generic']
+# Enum for DecoderFlavor
+class DecoderFlavor(Enum): vals = ['Generic']
 
 class ArmISA(BaseISA):
     type = 'ArmISA'
@@ -55,7 +55,8 @@ class ArmISA(BaseISA):
     system = Param.System(Parent.any, "System this ISA object belongs to")
 
     pmu = Param.ArmPMU(NULL, "Performance Monitoring Unit")
-    decoderFlavour = Param.DecoderFlavour('Generic', "Decoder flavour specification")
+    decoderFlavor = Param.DecoderFlavor(
+            'Generic', "Decoder flavor specification")
 
     # If no MIDR value is provided, 0x0 is treated by gem5 as follows:
     # When 'highest_el_is_64' (AArch64 support) is:

src/arch/arm/decoder.cc

@@ -55,8 +55,7 @@ namespace ArmISA
 GenericISA::BasicDecodeCache Decoder::defaultCache;
 
 Decoder::Decoder(ISA* isa)
-    : data(0), fpscrLen(0), fpscrStride(0),
-      decoderFlavour(isa->decoderFlavour())
+    : data(0), fpscrLen(0), fpscrStride(0), decoderFlavor(isa->decoderFlavor())
 {
     reset();
 

src/arch/arm/decoder.hh

@@ -50,7 +50,7 @@
 #include "arch/generic/decode_cache.hh"
 #include "base/types.hh"
 #include "cpu/static_inst.hh"
-#include "enums/DecoderFlavour.hh"
+#include "enums/DecoderFlavor.hh"
 
 namespace ArmISA
 {
@@ -78,7 +78,7 @@ class Decoder
      */
     int sveLen;
 
-    Enums::DecoderFlavour decoderFlavour;
+    Enums::DecoderFlavor decoderFlavor;
 
     /// A cache of decoded instruction objects.
     static GenericISA::BasicDecodeCache defaultCache;

src/arch/arm/isa.cc

@@ -62,7 +62,7 @@ namespace ArmISA
 {
 
 ISA::ISA(Params *p) : BaseISA(p), system(NULL),
-    _decoderFlavour(p->decoderFlavour), _vecRegRenameMode(Enums::Full),
+    _decoderFlavor(p->decoderFlavor), _vecRegRenameMode(Enums::Full),
     pmu(p->pmu), haveGICv3CPUInterface(false), impdefAsNop(p->impdef_nop),
     afterStartup(false)
 {

src/arch/arm/isa.hh

@@ -52,9 +52,9 @@
 #include "arch/generic/isa.hh"
 #include "arch/generic/traits.hh"
 #include "debug/Checkpoint.hh"
+#include "enums/DecoderFlavor.hh"
 #include "enums/VecRegRenameMode.hh"
 #include "sim/sim_object.hh"
-#include "enums/DecoderFlavour.hh"
 
 struct ArmISAParams;
 struct DummyArmISADeviceParams;
@@ -71,7 +71,7 @@ namespace ArmISA
         ArmSystem *system;
 
         // Micro Architecture
-        const Enums::DecoderFlavour _decoderFlavour;
+        const Enums::DecoderFlavor _decoderFlavor;
         const Enums::VecRegRenameMode _vecRegRenameMode;
 
         /** Dummy device for to handle non-existing ISA devices */
@@ -745,7 +745,7 @@ namespace ArmISA
 
         void startup(ThreadContext *tc);
 
-        Enums::DecoderFlavour decoderFlavour() const { return _decoderFlavour; }
+        Enums::DecoderFlavor decoderFlavor() const { return _decoderFlavor; }
 
         /** Getter for haveGICv3CPUInterface */
         bool haveGICv3CpuIfc() const

src/arch/arm/isa/formats/aarch64.isa

@@ -3010,10 +3010,10 @@ let {{
     decoder_output ='''
 namespace Aarch64
 {'''
-    for decoderFlavour, type_dict in decoders.iteritems():
+    for decoderFlavor, type_dict in decoders.iteritems():
         decoder_output +='''
 template StaticInstPtr decodeFpAdvSIMD<%(df)sDecoder>(ExtMachInst machInst);
-''' % { "df" : decoderFlavour }
+''' % { "df" : decoderFlavor }
     decoder_output +='''
 }'''
 }};
@@ -3096,7 +3096,7 @@ def format Aarch64() {{
             return decodeGem5Ops(machInst);
         } else {
             // bit 27:25=111
-            switch(decoderFlavour){
+            switch(decoderFlavor){
             default:
                 return decodeFpAdvSIMD<GenericDecoder>(machInst);
             }

src/arch/arm/isa/includes.isa

@@ -68,7 +68,7 @@ output header {{
 #include "arch/arm/insts/sve_mem.hh"
 #include "arch/arm/insts/vfp.hh"
 #include "arch/arm/isa_traits.hh"
-#include "enums/DecoderFlavour.hh"
+#include "enums/DecoderFlavor.hh"
 #include "mem/packet.hh"
 #include "sim/faults.hh"
 

src/arch/arm/isa/insts/neon64.isa

@@ -3388,11 +3388,11 @@ let {{
     threeRegScrambleInstX("zip2", "Zip2QX", "SimdAluOp", unsignedTypes, 4,
                           zipCode % "eCount / 2")
 
-    for decoderFlavour, type_dict in decoders.iteritems():
+    for decoderFlavor, type_dict in decoders.iteritems():
         header_output += '''
-        class %(decoder_flavour)sDecoder {
+        class %(decoder_flavor)sDecoder {
         public:
-        ''' % { "decoder_flavour" : decoderFlavour }
+        ''' % { "decoder_flavor" : decoderFlavor }
         for type,name in type_dict.iteritems():
             header_output += '''
             template<typename Elem> using %(type)s = %(new_name)s<Elem>;''' % {

src/dev/arm/FlashDevice.py

@@ -56,7 +56,7 @@ class FlashDevice(AbstractNVM):
     # disk page size is 2 kB. This is the most commonly used page size in
     # flash devices
     page_size = Param.MemorySize("2kB", "Size of one disk page")
-    # There are many GC flavours. It is impossible to cover them all; this
+    # There are many GC flavors. It is impossible to cover them all; this
     # parameter enables the approximation of different GC algorithms
     GC_active = Param.Percent(50, "Percentage of the time (in whole numbers) \
         that the GC is activated if a block is full")