derek/gem5
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

arch,cpu: Make the CPU's ISA parameter type BaseISA.

Browse Source 
This is mostly only a superficial change since the isa parameter is
then dynamic cast to the ISA specific version inside the various
consumers, currently the SimpleThread, O3CPU and Decoder classes. If
those aren't being used, for instance in the fast model CPUs, then you
can use a different ISA implementation without any type clashes.

Change-Id: I2226ef60f9a471ae51b8bfce8683033f7854197a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25009
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
2020-02-03 17:08:18 -08:00
parent d1e2f18230
commit eae03bbc9d
5 changed files with 24 additions and 21 deletions
Download Patch File Download Diff File Expand all files Collapse all files

9
src/cpu/BaseCPU.py
View File

@@ -66,37 +66,30 @@ if buildEnv['TARGET_ISA'] == 'alpha':
from m5.objects.AlphaTLB import AlphaDTB as ArchDTB, AlphaITB as ArchITB
from m5.objects.AlphaInterrupts import AlphaInterrupts as ArchInterrupts
from m5.objects.AlphaISA import AlphaISA as ArchISA
ArchISAsParam = VectorParam.AlphaISA
elif buildEnv['TARGET_ISA'] == 'sparc':
from m5.objects.SparcTLB import SparcTLB as ArchDTB, SparcTLB as ArchITB
from m5.objects.SparcInterrupts import SparcInterrupts as ArchInterrupts
from m5.objects.SparcISA import SparcISA as ArchISA
ArchISAsParam = VectorParam.SparcISA
elif buildEnv['TARGET_ISA'] == 'x86':
from m5.objects.X86TLB import X86TLB as ArchDTB, X86TLB as ArchITB
from m5.objects.X86LocalApic import X86LocalApic as ArchInterrupts
from m5.objects.X86ISA import X86ISA as ArchISA
ArchISAsParam = VectorParam.X86ISA
elif buildEnv['TARGET_ISA'] == 'mips':
from m5.objects.MipsTLB import MipsTLB as ArchDTB, MipsTLB as ArchITB
from m5.objects.MipsInterrupts import MipsInterrupts as ArchInterrupts
from m5.objects.MipsISA import MipsISA as ArchISA
ArchISAsParam = VectorParam.MipsISA
elif buildEnv['TARGET_ISA'] == 'arm':
from m5.objects.ArmTLB import ArmDTB as ArchDTB, ArmITB as ArchITB
from m5.objects.ArmInterrupts import ArmInterrupts as ArchInterrupts
from m5.objects.ArmISA import ArmISA as ArchISA
ArchISAsParam = VectorParam.ArmISA
elif buildEnv['TARGET_ISA'] == 'power':
from m5.objects.PowerTLB import PowerTLB as ArchDTB, PowerTLB as ArchITB
from m5.objects.PowerInterrupts import PowerInterrupts as ArchInterrupts
from m5.objects.PowerISA import PowerISA as ArchISA
ArchISAsParam = VectorParam.PowerISA
elif buildEnv['TARGET_ISA'] == 'riscv':
from m5.objects.RiscvTLB import RiscvTLB as ArchDTB, RiscvTLB as ArchITB
from m5.objects.RiscvInterrupts import RiscvInterrupts as ArchInterrupts
from m5.objects.RiscvISA import RiscvISA as ArchISA
ArchISAsParam = VectorParam.RiscvISA
else:
print("Don't know what object types to use for ISA %s" %
buildEnv['TARGET_ISA'])
@@ -176,7 +169,7 @@ class BaseCPU(ClockedObject):
if buildEnv['TARGET_ISA'] == 'power':
UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
interrupts = VectorParam.BaseInterrupts([], "Interrupt Controller")
isa = ArchISAsParam([], "ISA instance")
isa = VectorParam.BaseISA([], "ISA instance")
max_insts_all_threads = Param.Counter(0,
"terminate when all threads have reached this inst count")

12
src/cpu/o3/cpu.cc
View File

@@ -109,9 +109,6 @@ FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
iew(this, params),
commit(this, params),
/* It is mandatory that all SMT threads use the same renaming mode as
* they are sharing registers and rename */
vecMode(RenameMode<TheISA::ISA>::init(params->isa[0])),
regFile(params->numPhysIntRegs,
params->numPhysFloatRegs,
params->numPhysVecRegs,
@@ -141,6 +138,12 @@ FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
system(params->system),
lastRunningCycle(curCycle())
{
auto *the_isa = dynamic_cast<TheISA::ISA *>(params->isa[0]);
assert(the_isa);
/* It is mandatory that all SMT threads use the same renaming mode as
* they are sharing registers and rename */
vecMode = RenameMode<TheISA::ISA>::init(the_isa);
if (!params->switched_out) {
_status = Running;
} else {
@@ -220,7 +223,8 @@ FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
// Setup the rename map for whichever stages need it.
for (ThreadID tid = 0; tid < numThreads; tid++) {
isa[tid] = params->isa[tid];
isa[tid] = dynamic_cast<TheISA::ISA *>(params->isa[tid]);
assert(isa[tid]);
assert(RenameMode<TheISA::ISA>::equalsInit(isa[tid], isa[0]));
// Only Alpha has an FP zero register, so for other ISAs we

3
src/cpu/o3/fetch_impl.hh
View File

@@ -142,7 +142,8 @@ DefaultFetch<Impl>::DefaultFetch(O3CPU *_cpu, DerivO3CPUParams *params)
branchPred = params->branchPred;
for (ThreadID tid = 0; tid < numThreads; tid++) {
decoder[tid] = new TheISA::Decoder(params->isa[tid]);
decoder[tid] = new TheISA::Decoder(
dynamic_cast<TheISA::ISA *>(params->isa[tid]));
// Create space to buffer the cache line data,
// which may not hold the entire cache line.
fetchBuffer[tid] = new uint8_t[fetchBufferSize];

17
src/cpu/simple_thread.cc
View File

@@ -75,24 +75,29 @@ using namespace std;
// constructor
SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
Process *_process, BaseTLB *_itb,
BaseTLB *_dtb, TheISA::ISA *_isa)
: ThreadState(_cpu, _thread_num, _process), isa(_isa),
BaseTLB *_dtb, BaseISA *_isa)
: ThreadState(_cpu, _thread_num, _process),
isa(dynamic_cast<TheISA::ISA *>(_isa)),
predicate(true), memAccPredicate(true),
comInstEventQueue("instruction-based event queue"),
system(_sys), itb(_itb), dtb(_dtb), decoder(TheISA::Decoder(_isa))
system(_sys), itb(_itb), dtb(_dtb), decoder(TheISA::Decoder(isa))
{
assert(isa);
clearArchRegs();
quiesceEvent = new EndQuiesceEvent(this);
}
SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
BaseTLB *_itb, BaseTLB *_dtb,
TheISA::ISA *_isa, bool use_kernel_stats)
: ThreadState(_cpu, _thread_num, NULL), isa(_isa),
BaseISA *_isa, bool use_kernel_stats)
: ThreadState(_cpu, _thread_num, NULL),
isa(dynamic_cast<TheISA::ISA *>(_isa)),
predicate(true), memAccPredicate(true),
comInstEventQueue("instruction-based event queue"),
system(_sys), itb(_itb), dtb(_dtb), decoder(TheISA::Decoder(_isa))
system(_sys), itb(_itb), dtb(_dtb), decoder(TheISA::Decoder(isa))
{
assert(isa);
quiesceEvent = new EndQuiesceEvent(this);
clearArchRegs();

4
src/cpu/simple_thread.hh
View File

@@ -144,12 +144,12 @@ class SimpleThread : public ThreadState, public ThreadContext
// constructor: initialize SimpleThread from given process structure
// FS
SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
BaseTLB *_itb, BaseTLB *_dtb, TheISA::ISA *_isa,
BaseTLB *_itb, BaseTLB *_dtb, BaseISA *_isa,
bool use_kernel_stats = true);
// SE
SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
Process *_process, BaseTLB *_itb, BaseTLB *_dtb,
TheISA::ISA *_isa);
BaseISA *_isa);
virtual ~SimpleThread() {}