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arch-power: Add move condition field instructions

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This adds the following instructions.
  * Move to CR from XER Extended (mcrxrx)
  * Move To One Condition Register Field (mtocrf)
  * Move From One Condition Register Field (mfocrf)

Change-Id: I5014160d77b1b759c1cb8cba34e6dd20eb2b5205
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40936
Reviewed-by: Boris Shingarov <shingarov@labware.com>
Maintainer: Boris Shingarov <shingarov@labware.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Sandipan Das
2021-02-06 17:22:23 +05:30
committed by Boris Shingarov
parent c8207e2286
commit 09ec394844
1 changed files with 24 additions and 0 deletions
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24
src/arch/power/isa/decoder.isa
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@@ -638,6 +638,14 @@ decode PO default Unknown::unknown() {
567: LoadIndexUpdateOp::lfsux({{ Ft_sf = Mem_sf; }});
570: IntLogicOp::cnttzd({{ Ra = findTrailingZeros(Rs); }}, true);
576: IntOp::mcrxrx({{
uint8_t res;
Xer xer = XER;
res = (xer.ov << 3) | (xer.ov32 << 2) | (xer.ca << 1) | xer.ca32;
CR = insertCRField(CR, BF, res);
}});
598: MiscOp::sync({{ }}, [ IsReadBarrier, IsWriteBarrier ]);
599: LoadIndexOp::lfdx({{ Ft = Mem_df; }});
631: LoadIndexUpdateOp::lfdux({{ Ft = Mem_df; }});
@@ -980,6 +988,14 @@ decode PO default Unknown::unknown() {
format IntOp {
19: decode S {
0: mfcr({{ Rt = CR; }});
1: mfocrf({{
int count = popCount(FXM);
uint64_t mask = 0xf << (4 * findMsbSet(FXM));
if (count == 1) {
Rt = CR & mask;
}
}});
}
144: decode S {
@@ -992,6 +1008,14 @@ decode PO default Unknown::unknown() {
}
CR = (Rs & mask) | (CR & ~mask);
}});
1: mtocrf({{
int count = popCount(FXM);
uint32_t mask = 0xf << (4 * findMsbSet(FXM));
if (count == 1) {
CR = (Rs & mask) | (CR & ~mask);
}
}});
}
339: decode SPR {