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arch-power: Fix move condition field instructions

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This introduces the S field for X form instructions which
is used to specify signed versus unsigned comparison. The
Power ISA does not specify a formal name for the third
1-bit opcode field required for decoding XFX form move to
and from CR field instructions, the S field can be used
to achieve the same as it has the same span and position.
This fixes the following instructions.
  * Move To Condition Register Fields (mtcrf)
  * Move From Condition Register (mfcr)

Change-Id: I8d291f707cd063781f0497f7226bebfc47bd9e63
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40935
Reviewed-by: Boris Shingarov <shingarov@labware.com>
Maintainer: Boris Shingarov <shingarov@labware.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Sandipan Das
2021-02-06 17:22:19 +05:30
committed by Boris Shingarov
parent 57181ee613
commit c8207e2286
2 changed files with 14 additions and 9 deletions
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1
src/arch/power/isa/bitfields.isa
View File

@@ -73,6 +73,7 @@ def bitfield SPR <20:11>;
// FXM field for mtcrf instruction
def bitfield FXM <19:12>;
def bitfield S <20>;
// Branch fields
def bitfield BO <25:21>;

22
src/arch/power/isa/decoder.isa
View File

@@ -978,17 +978,21 @@ decode PO default Unknown::unknown() {
default: decode XFX_XO {
format IntOp {
19: mfcr({{ Rt = CR; }});
19: decode S {
0: mfcr({{ Rt = CR; }});
}
144: mtcrf({{
uint32_t mask = 0;
for (int i = 0; i < 8; ++i) {
if (((FXM >> i) & 0x1) == 0x1) {
mask |= 0xf << (4 * i);
144: decode S {
0: mtcrf({{
uint32_t mask = 0;
for (int i = 0; i < 8; ++i) {
if (bits(FXM, i)) {
mask |= 0xf << (4 * i);
}
}
}
CR = (Rs & mask) | (CR & ~mask);
}});
CR = (Rs & mask) | (CR & ~mask);
}});
}
339: decode SPR {
0x20: mfxer({{ Rt = XER; }});