derek/gem5
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

stdlib: Update the LupvBoard to use 'requires'

Browse Source 
Usage of this function was previously avoided due to a bug which has
since been fixed:
https://gem5-review.googlesource.com/c/public/gem5/+/53003

Change-Id: Idc76ca26d02dcfbb290cebcca297e50e905d8e6d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53084
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
This commit is contained in:
Bobby R. Bruce
2021-11-22 15:47:36 -08:00
committed by melissa jost
parent d05145c5cb
commit 05878dc581
1 changed files with 4 additions and 7 deletions
Download Patch File Download Diff File Expand all files Collapse all files

11
src/python/gem5/components/boards/experimental/lupv_board.py
View File

@@ -33,7 +33,7 @@ from ...processors.abstract_processor import AbstractProcessor
from ...memory.abstract_memory_system import AbstractMemorySystem
from ...cachehierarchies.abstract_cache_hierarchy import AbstractCacheHierarchy
from ....isas import ISA
from ....runtime import get_runtime_isa
from ....utils.requires import requires
import m5
from m5.objects import (
@@ -89,15 +89,12 @@ class LupvBoard(AbstractBoard):
cache_hierarchy: AbstractCacheHierarchy,
) -> None:
super().__init__(clk_freq, processor, memory, cache_hierarchy)
if get_runtime_isa() != ISA.RISCV:
raise EnvironmentError(
"RiscvBoard will only work with the RISC-V ISA. Please"
" recompile gem5 with ISA=RISCV."
)
requires(isa_required=ISA.RISCV)
if cache_hierarchy.is_ruby():
raise EnvironmentError("RiscvBoard is not compatible with Ruby")
super().__init__(clk_freq, processor, memory, cache_hierarchy)
@overrides(AbstractBoard)
def _setup_board(self) -> None: