From 05878dc5815305b625e4f237ff7c44b4964c4062 Mon Sep 17 00:00:00 2001 From: "Bobby R. Bruce" Date: Mon, 22 Nov 2021 15:47:36 -0800 Subject: [PATCH] stdlib: Update the LupvBoard to use 'requires' Usage of this function was previously avoided due to a bug which has since been fixed: https://gem5-review.googlesource.com/c/public/gem5/+/53003 Change-Id: Idc76ca26d02dcfbb290cebcca297e50e905d8e6d Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53084 Maintainer: Bobby Bruce Tested-by: kokoro Reviewed-by: Jason Lowe-Power --- .../gem5/components/boards/experimental/lupv_board.py | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/src/python/gem5/components/boards/experimental/lupv_board.py b/src/python/gem5/components/boards/experimental/lupv_board.py index e2787d5973..d14326ced3 100644 --- a/src/python/gem5/components/boards/experimental/lupv_board.py +++ b/src/python/gem5/components/boards/experimental/lupv_board.py @@ -33,7 +33,7 @@ from ...processors.abstract_processor import AbstractProcessor from ...memory.abstract_memory_system import AbstractMemorySystem from ...cachehierarchies.abstract_cache_hierarchy import AbstractCacheHierarchy from ....isas import ISA -from ....runtime import get_runtime_isa +from ....utils.requires import requires import m5 from m5.objects import ( @@ -89,15 +89,12 @@ class LupvBoard(AbstractBoard): cache_hierarchy: AbstractCacheHierarchy, ) -> None: - super().__init__(clk_freq, processor, memory, cache_hierarchy) - if get_runtime_isa() != ISA.RISCV: - raise EnvironmentError( - "RiscvBoard will only work with the RISC-V ISA. Please" - " recompile gem5 with ISA=RISCV." - ) + requires(isa_required=ISA.RISCV) if cache_hierarchy.is_ruby(): raise EnvironmentError("RiscvBoard is not compatible with Ruby") + super().__init__(clk_freq, processor, memory, cache_hierarchy) + @overrides(AbstractBoard) def _setup_board(self) -> None: