DRAMSys

doc.bib

@@ -72,4 +72,52 @@
   doi       = {10.1109/SAMOS.2017.8344612},
 }
 
+@InProceedings{Steiner2020,
+  author    = {Steiner, Lukas and Jung, Matthias and Prado, Felipe S. and Bykov, Kirill and Wehn, Norbert},
+  booktitle = {Embedded Computer Systems: Architectures, Modeling, and Simulation},
+  title     = {DRAMSys4.0: A Fast and Cycle-Accurate SystemC/TLM-Based DRAM Simulator},
+  year      = {2020},
+  address   = {Cham},
+  editor    = {Orailoglu, Alex and Jung, Matthias and Reichenbach, Marc},
+  pages     = {110--126},
+  publisher = {Springer International Publishing},
+  abstract  = {The simulation of DRAMs (Dynamic Random Access Memories) on system level requires highly accurate models due to their complex timing and power behavior. However, conventional cycle-accurate DRAM models often become the bottleneck for the overall simulation speed. A promising alternative are DRAM simulation models based on Transaction Level Modeling, which can be fast and accurate at the same time. In this paper we present DRAMSys4.0, which is, to the best of our knowledge, the fastest cycle-accurate open-source DRAM simulator and has a large range of functionalities. DRAMSys4.0 includes a novel simulator architecture that enables a fast adaptation to new DRAM standards using a Domain Specific Language. We present optimization techniques to achieve a high simulation speed while maintaining full temporal accuracy. Finally, we provide a detailed survey and comparison of the most prominent cycle-accurate open-source DRAM simulators with regard to their supported features, analysis capabilities and simulation speed.},
+  isbn      = {978-3-030-60939-9},
+}
+
+@Book{Jung2017,
+  author    = {Jung, M.},
+  publisher = {Technische Universit{\"a}t Kaiserslautern},
+  title     = {System-level Modeling, Analysis and Optimization of DRAM Memories and Controller Architectures},
+  year      = {2017},
+  isbn      = {9783959740517},
+  series    = {Forschungsberichte Mikroelektronik},
+}
+
+@Article{Binkert2011,
+  author     = {Binkert, Nathan and Beckmann, Bradford and Black, Gabriel and Reinhardt, Steven K. and Saidi, Ali and Basu, Arkaprava and Hestness, Joel and Hower, Derek R. and Krishna, Tushar and Sardashti, Somayeh and Sen, Rathijit and Sewell, Korey and Shoaib, Muhammad and Vaish, Nilay and Hill, Mark D. and Wood, David A.},
+  journal    = {SIGARCH Comput. Archit. News},
+  title      = {The Gem5 Simulator},
+  year       = {2011},
+  issn       = {0163-5964},
+  month      = {aug},
+  number     = {2},
+  volume     = {39},
+  abstract   = {The gem5 simulation infrastructure is the merger of the best aspects of the M5 [4] and GEMS [9] simulators. M5 provides a highly configurable simulation framework, multiple ISAs, and diverse CPU models. GEMS complements these features with a detailed and exible memory system, including support for multiple cache coherence protocols and interconnect models. Currently, gem5 supports most commercial ISAs (ARM, ALPHA, MIPS, Power, SPARC, and x86), including booting Linux on three of them (ARM, ALPHA, and x86).The project is the result of the combined efforts of many academic and industrial institutions, including AMD, ARM, HP, MIPS, Princeton, MIT, and the Universities of Michigan, Texas, and Wisconsin. Over the past ten years, M5 and GEMS have been used in hundreds of publications and have been downloaded tens of thousands of times. The high level of collaboration on the gem5 project, combined with the previous success of the component parts and a liberal BSD-like license, make gem5 a valuable full-system simulation tool.},
+  address    = {New York, NY, USA},
+  doi        = {10.1145/2024716.2024718},
+  issue_date = {May 2011},
+  numpages   = {7},
+  publisher  = {Association for Computing Machinery},
+  url        = {https://doi.org/10.1145/2024716.2024718},
+}
+
+@InProceedings{Jung2017a,
+  author    = {Jung, Matthias and Kraft, Kira and Wehn, Norbert},
+  booktitle = {2017 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS)},
+  title     = {A new state model for DRAMs using Petri Nets},
+  year      = {2017},
+  doi       = {10.1109/SAMOS.2017.8344631},
+}
+
 @Comment{jabref-meta: databaseType:bibtex;}

inc/3.systemc.tex

@@ -31,7 +31,7 @@ GPs are transferred as references, avoiding the need to copy them between the mo
 \begin{figure}[!ht]
 \begin{center}
 \tikzfig{img/tlm}
-\caption{Forward and backward path between TLM sockets\cite{Menard2017}. $\blacksquare$ denotes a initiator socket, $\square$ denotes a target socket.}
+\caption{Forward and backward path between TLM sockets\cite{Menard2017}. $\blacksquare$ denotes an initiator socket, $\square$ denotes a target socket.}
 \label{fig:tlm}
 \end{center}
 \end{figure}
@@ -68,4 +68,4 @@ SystemC also supports additional user-defined phases through its \texttt{DECLARE
 In contrast to the TLM-LT protocol, TLM-AT makes it possible model pipelining of transactions; multiple transactions can be processed by a target at one time.
 The responses also do not need to be in the same order as the initiator has sent them: they can be \textit{out out order}.
 
-The TLM-AT protol is the used protocol to model the initiator and the cache model in section \ref{sec:implementation} of this thesis.
+The TLM-AT protol is the used protocol to implement the processor model and the cache model in section \ref{sec:implementation} of this thesis.

inc/5.dramsys.tex

@@ -1,2 +1,41 @@
 \section{DRAMSys}
 \label{sec:dramsys}
+
+DRAMSys is an open-source design space exploration framework, capable of simulating the latest \revabbr{Joint Electron Device Engineering Council}{JEDEC} DRAM standards.
+It is optimized to achieve high simulation speeds and utilizes the TLM-AT coding style while still achieving cycle accurate results\cite{Steiner2020}.
+
+DRAMSys is composed of an arbitration \& mapping unit (also called arbiter) and independent channel controllers with a DRAM device each.
+The general architecture of DRAMSys is illustrated in figure \ref{fig:dramsys}.
+
+\begin{figure}[!ht]
+\begin{center}
+\includegraphics{img/dramsys.pdf}
+\caption{Structure of DRAMSys\cite{Jung2017}.}
+\label{fig:dramsys}
+\end{center}
+\end{figure}
+
+Several initiators can be connected to the arbiter, sending requests to the DRAM subsystem.
+An initiator can either be a sophisticated processor model like the gem5 out of order processor model\cite{Binkert2011} or a trace player that simply replays a trace file containing a sequence of memory requests and timestamps.
+
+To support a large variety of DRAM standards robustly and error-free, DRAMSys uses a formal domain specific language based on petri nets called DRAMml.
+This language includes a standards timing dependencies between all DRAM commands and compiles to source code of the internal timing checkers that ensure compliance to the specific standard \cite{Jung2017a}.
+
+Because a single memory access can cause the issuance of multiple commands (e.g. precharge (\texttt{PRE}), activate (\texttt{ACT}), read (\texttt{RD}) or write (\texttt{WR})), the four phase handshake of the TLM-AT protocol is not sufficient enough.
+Therefore, a custom TLM protocol called DRAM-AT is used as the communication protocol between the channel controller and the DRAM device \cite{Steiner2020}.
+
+% Evtl TA falls Bilder genutzt werden?
+DRAMSys also provides the so-called \textit{Trace Analyzer}, a graphical tool that visualizes database files created by DRAMSys.
+It shows the \texttt{REQ} and \texttt{RESP} phases between the initiator and the arbiter, the occupation of the command bus and data bus as well as represenstations of the different phases in the DRAM banks.
+An example trace database, visualized in the Trace Analyzer is shown in figure \ref{fig:traceanalyzer}.
+Furthermore, the Trace Analyzer is capable of calculating numerous metrics and creating plots of interesting characteristics.
+
+\begin{figure}[!ht]
+\begin{center}
+\includegraphics{img/traceanalyzer.pdf}
+\caption{Exemplary visualization of a trace database in the Trace Analyzer.}
+\label{fig:traceanalyzer}
+\end{center}
+\end{figure}
+
+In section \ref{sec:implementation} of this thesis a special trace player for DRAMSys will be developed.

inc/6.implementation.tex

@@ -77,7 +77,7 @@ This instruction count is used to approximate the delay between the memory acces
 As of writing this thesis, there is no application binary interface for analysis tools defined in the DrCacheSim-Framework.
 Therefore it is not possible to load the DRAMTracer tool as a shared library but rather it is required to modify the DynamoRIO source code to integrate the tool.
 
-\subsection{DbiPlayer Architecture}
+\subsection{Trace Player Architecture}
 \label{sec:dbiplayer_architecture}
 
 This section covers the general architecture of the DbiPlayer, the new trace player for DRAMSys that replays the captured trace files.
@@ -113,7 +113,7 @@ This hierarchy is also reflected in the DbiPlayer as shown in Figure \ref{fig:db
 \end{figure}
 \end{landscape}
 
-\subsection{DbiPlayer Functionality}
+\subsection{Trace Player Functionality}
 \label{sec:dbiplayer_functionality}
 
 With the overall architecture of the initiator introduced, this section explains the internal functionality of the DbiPlayer and its threads.