42 lines
2.7 KiB
TeX
42 lines
2.7 KiB
TeX
\section{DRAMSys}
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\label{sec:dramsys}
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DRAMSys is an open-source design space exploration framework, capable of simulating the latest \revabbr{Joint Electron Device Engineering Council}{JEDEC} DRAM standards.
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It is optimized to achieve high simulation speeds and utilizes the TLM-AT coding style while still achieving cycle accurate results\cite{Steiner2020}.
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DRAMSys is composed of an arbitration \& mapping unit (also called arbiter) and independent channel controllers with a DRAM device each.
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The general architecture of DRAMSys is illustrated in figure \ref{fig:dramsys}.
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\begin{figure}[!ht]
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\begin{center}
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\includegraphics{img/dramsys.pdf}
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\caption{Structure of DRAMSys\cite{Jung2017}.}
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\label{fig:dramsys}
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\end{center}
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\end{figure}
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Several initiators can be connected to the arbiter, sending requests to the DRAM subsystem.
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An initiator can either be a sophisticated processor model like the gem5 out of order processor model\cite{Binkert2011} or a trace player that simply replays a trace file containing a sequence of memory requests and timestamps.
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To support a large variety of DRAM standards robustly and error-free, DRAMSys uses a formal domain specific language based on petri nets called DRAMml.
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This language includes a standards timing dependencies between all DRAM commands and compiles to source code of the internal timing checkers that ensure compliance to the specific standard \cite{Jung2017a}.
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Because a single memory access can cause the issuance of multiple commands (e.g. precharge (\texttt{PRE}), activate (\texttt{ACT}), read (\texttt{RD}) or write (\texttt{WR})), the four phase handshake of the TLM-AT protocol is not sufficient enough.
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Therefore, a custom TLM protocol called DRAM-AT is used as the communication protocol between the channel controller and the DRAM device \cite{Steiner2020}.
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% Evtl TA falls Bilder genutzt werden?
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DRAMSys also provides the so-called \textit{Trace Analyzer}, a graphical tool that visualizes database files created by DRAMSys.
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It shows the \texttt{REQ} and \texttt{RESP} phases between the initiator and the arbiter, the occupation of the command bus and data bus as well as represenstations of the different phases in the DRAM banks.
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An example trace database, visualized in the Trace Analyzer is shown in figure \ref{fig:traceanalyzer}.
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Furthermore, the Trace Analyzer is capable of calculating numerous metrics and creating plots of interesting characteristics.
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\begin{figure}[!ht]
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\begin{center}
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\includegraphics{img/traceanalyzer.pdf}
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\caption{Exemplary visualization of a trace database in the Trace Analyzer.}
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\label{fig:traceanalyzer}
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\end{center}
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\end{figure}
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In section \ref{sec:implementation} of this thesis a special trace player for DRAMSys will be developed.
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