\section{DRAMSys}
\label{sec:dramsys}

DRAMSys is an open-source design space exploration framework, capable of simulating the latest \revabbr{Joint Electron Device Engineering Council}{JEDEC} DRAM standards.
It is optimized to achieve high simulation speeds and utilizes the TLM-AT coding style while still achieving cycle accurate results\cite{Steiner2020}.

DRAMSys is composed of an arbitration \& mapping unit (also called arbiter) and independent channel controllers with a DRAM device each.
The general architecture of DRAMSys is illustrated in figure \ref{fig:dramsys}.

\begin{figure}[!ht]
\begin{center}
\includegraphics{img/dramsys.pdf}
\caption{Structure of DRAMSys\cite{Jung2017}.}
\label{fig:dramsys}
\end{center}
\end{figure}

Several initiators can be connected to the arbiter, sending requests to the DRAM subsystem.
An initiator can either be a sophisticated processor model like the gem5 out of order processor model\cite{Binkert2011} or a trace player that simply replays a trace file containing a sequence of memory requests and timestamps.

To support a large variety of DRAM standards robustly and error-free, DRAMSys uses a formal domain specific language based on petri nets called DRAMml.
This language includes a standards timing dependencies between all DRAM commands and compiles to source code of the internal timing checkers that ensure compliance to the specific standard \cite{Jung2017a}.

Because a single memory access can cause the issuance of multiple commands (e.g. precharge (\texttt{PRE}), activate (\texttt{ACT}), read (\texttt{RD}) or write (\texttt{WR})), the four phase handshake of the TLM-AT protocol is not sufficient enough.
Therefore, a custom TLM protocol called DRAM-AT is used as the communication protocol between the channel controller and the DRAM device \cite{Steiner2020}.

% Evtl TA falls Bilder genutzt werden?
DRAMSys also provides the so-called \textit{Trace Analyzer}, a graphical tool that visualizes database files created by DRAMSys.
It shows the \texttt{REQ} and \texttt{RESP} phases between the initiator and the arbiter, the occupation of the command bus and data bus as well as represenstations of the different phases in the DRAM banks.
An example trace database, visualized in the Trace Analyzer is shown in figure \ref{fig:traceanalyzer}.
Furthermore, the Trace Analyzer is capable of calculating numerous metrics and creating plots of interesting characteristics.

\begin{figure}[!ht]
\begin{center}
\includegraphics{img/traceanalyzer.pdf}
\caption{Exemplary visualization of a trace database in the Trace Analyzer.}
\label{fig:traceanalyzer}
\end{center}
\end{figure}

In section \ref{sec:implementation} of this thesis a special trace player for DRAMSys will be developed.
