368 lines
12 KiB
Markdown
368 lines
12 KiB
Markdown
de.uni-kl.ems.dram.vp.system
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============================
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Generic DRAM controller simulator **DRAMSys** [1] and related tools.
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## Basic Setup
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In a terminal window execute the commands that follow.
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Go to your home directory.
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``` bash
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$ cd
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```
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Create a directory for your projects.
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``` bash
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$ mkdir projects
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```
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Clone the repository.
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``` bash
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$ git clone --recursive https://<user>@git.rhrk.uni-kl.de/EIT-Wehn/dram.vp.system.git
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```
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The *--recursive* flag tells git to initialize all submodules within the
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repository. **DRAMPower** [2] and **tinyxml** are examples third party
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repositories that were embedded within the source tree as submodules.
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It is possible to work with a **fork** of the official codebase. In that case,
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after pushing changes into your fork you should create a **pull request** in
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order to get your changes merged into to the official codebase.
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``` bash
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$ git clone --recursive https://<user>@git.rhrk.uni-kl.de/<user>/dram.vp.system.git
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```
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Also, the official repository must be added as a remote for your fork.
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``` bash
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$ git remote add upstream https://<user>@git.rhrk.uni-kl.de/EIT-Wehn/dram.vp.system.git
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$ git remote -v
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```
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After a pull request being accepted and merged into the official repository
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you should get your fork updated.
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``` bash
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$ git fetch upstream
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$ git checkout master
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$ git merge upstream/master
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$ git push origin HEAD
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```
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After cloning go to the project directory.
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``` bash
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$ cd dram.vp.system
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```
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### With QTCreator
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Execute the *QTCreator*.
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``` bash
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$ qtcreator &
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```
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Use the menu bar and open the DRAMSys project.
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**File -> Open Project -> dram.vp.sys/dram/dramSys/dramSys.pro**
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When you open the project for the first time a configuration window pops-up.
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Then click in **Configure Project** and after that **Build** the project.
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Repeat the procedure above and build the trace analyser project.
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**File -> Open Project -> dram.vp.sys/analyser/analyser/traceAnalizer.pro**
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To speedup the building process one can use the additional **make** option
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**-j[jobs]**. The command line below returns a good number to be passed to
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make as the number of jobs that can run simultaneously to improve the building
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time.
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``` bash
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$ cat /proc/cpuinfo | grep processor | wc -l
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```
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In the left bar go to **Projects -> Build & Run -> Build Steps -> Make**.
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Click in **Details** then **Make arguments** and add **-j** followed by the
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number you got.
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### Without QTCreator
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In case you prefer a command line interface to the QTCreator GUI you can also
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use **qmake** to generate a Makefile and then compile the project.
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``` bash
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$ cd dram
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$ mkdir build
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$ cd build
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$ qmake ../dramSys/dramSys.pro
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$ make
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```
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### DRAMSys Configuration
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The **dramSys** executable supports one argument which is a XML file that
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contains configurable aspects of the desired simulation. If no argument is
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passed through the command line a default configuration file will be loaded.
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The XML code below shows a typic configuration:
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``` xml
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<simulation>
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<simconfig>
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<Debug value="1"/>
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<DatabaseRecording value="1"/>
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<PowerAnalysis value="1"/>
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<NumberOfTracePlayers value="5"/>
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<NumberOfMemChannels value="1"/>
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</simconfig>
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<memspecs>
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<memspec src="../resources/configs/memspecs/WideIO.xml"></memspec>
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</memspecs>
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<addressmappings>
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<addressmapping src="../resources/configs/amconfigs/am_wideio.xml"></addressmapping>
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</addressmappings>
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<memconfigs>
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<memconfig src="../resources/configs/memconfigs/fifo.xml"/>
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</memconfigs>
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<tracesetups>
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<!-- Multiple trace setups are allowed for the same simulation setup -->
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<tracesetup id="fifo">
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<!--
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Specify here a trace file for each of the trace players. Trace
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players without a file will not generate transactions.
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It is also possible to choose "cklMhz" and the "bl" for every
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player.
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-->
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<device clkMhz="200">voco2.stl</device>
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<device clkMhz="200">voco2.stl</device>
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<device clkMhz="200">voco2.stl</device>
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</tracesetup>
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</tracesetups>
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</simulation>
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```
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Some configuration fields reference other XML files which contain more
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specialized chunks of the configuration like memory specification, address
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mapping and memory configurations.
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The XML configuration files are parsed by the program and the configuration
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details extracted are assigned to the correspondent attributes of the internal
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configuration structure.
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#### Simulation Setups
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Every possible combination of **memory specification**, **address mapping**
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and **memory configuration** corresponds to a **simulation setup**.
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Each of the **trace setups** listed in the configuration is added to every
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simulation setup.
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A **trace setup** is composed of an id string and one or more **devices**.
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A **device** configuration consists of two configuration fields - clkMhz
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(operation frequence for this device) and bl (burst length) - and a
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**trace file**.
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A **trace file** is a pre-recorded file containing memory transactions. All
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memory transactions have a timestamp that tells the simulator when they shall
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happen, a transaction type (e.g.: read, write) and a memory address.
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A **trace player** is the **equivalent** to bus master **device**, i.e. a
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device that locks a bus and generates memory transactions. The **device**
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section within a **trace setup** makes it is possible to add a trace file, and
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specify the operation frequence and the burst length as well, for each of the
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trace players. Trace players without a corresponding device configuration will
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not generate transactions.
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**DRAMSys** executes all the simulation setups within the configuration file
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providing **flexibility** for **exhaustive explorations.**
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#### Configuration File Sections
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The main configuration file is divided into self-contained sections, each of
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these sections is a set of logically related configuration aspects for the
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simulation.
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Below are listed the configuration sections and configuration fields.
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- **Simulator configuration**
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- *Debug* (boolean)
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- "1": enables debug output on console
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- "0": disables debug output
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- *DatabaseRecording* (boolean)
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- "1": enables trace file recording for the trace analyser tool
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- "0": disables trace file recording
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- *PowerAnalysis* (boolean)
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- "1": enables live power analysis with the DRAMPower tool
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- "0": disables power analysis
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- *NumberOfTracePlayers* (unsigned int)
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- Number of trace players
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- *NumberOfMemChannels* (unsigned int)
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- Number of memory channels
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- **Memory specification**
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A file with memory specifications. This information comes from datasheet and
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usually does not change.
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- **Address Mapping**
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XML files describe the address mapping to be used in the simulation.
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The file [am_wideio.xml](dram/resources/configs/amconfigs/am_wideio.xml) is
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a good example.
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``` xml
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<addressmapping>
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<channel from="27" to="28"/>
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<row from="14" to="26"/>
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<column from="7" to="13"/>
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<bank from="4" to="6" />
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<bytes from="0" to="3" />
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</addressmapping>
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```
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``` xml
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<addressmapping>
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<channel from="27" to="28"/>
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<column from="20" to="26"/>
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<row from="7" to="19"/>
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<bank from="4" to="6" />
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<bytes from="0" to="3" />
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</addressmapping>
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```
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- **Memory Configuration**
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The content of [fifo.xml](dram/resources/configs/memconfigs/fifo.xml) is
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presented below as an example.
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``` xml
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<memconfig>
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<BankwiseLogic value="0"/>
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<OpenPagePolicy value="1"/>
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<MaxNrOfTransactions value="8"/>
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<Scheduler value="FIFO_STRICT"/>
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<Capsize value="5"/>
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<PowerDownMode value="TimeoutSREF"/>
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<PowerDownTimeout value="100"/>
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<!-- Error Modelling -->
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<ErrorChipSeed value="42"/>
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<ErrorCSVFile value="../src/error/error_new.csv"/>
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<ErrorStoreMode value="NoStorage"/>
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</memconfig>
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```
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- *BankwiseLogic* (boolean)
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- "1": perform bankwise-refresh [3] and bankwise-powerdown [4]
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- "0": do not perform bankwise operations
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- *OpenPagePolicy* (boolean)
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- "1": use open page precharge policy
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- "0": do not use open page precharge policy
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- *MaxNrOfTransactions* (unsigned int)
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- Maximum number of transactions.
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- *Scheduler* (string)
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- "FIFO": first in, first out
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- "FIFO_STRICT": out-of-order treatment of queue elements not allowed
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- "FR_FCFS": first-come, first-served
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- *Capsize* (unsigned int)
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- Capacitor cell size.
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- *PowerDownMode* (enum EPowerDownMode)
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- "NoPowerDown": no power down mode (active idle)
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- "Staggered": staggered power down policy [5]
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- "TimeoutPDN": precharge idle
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- "TimeoutSREF": self refresh
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- *Buswidth* (unsigned int)
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- Bus width in bits.
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- *ReadWriteGrouping* (boolean)
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- "1": enable read writing grouping
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- "0": disable read writing grouping
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- *ReorderBuffer* (boolean)
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- "1": use reordering buffer
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- "0": do not use reordering buffer
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- *ErrorChipSeed* (unsigned int)
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- Seed to initialize the random error generator.
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- *ErrorCSVFile* (string)
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- CSV file with error injection information.
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- *ErrorStoreMode* (enum ErrorStorageMode)
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- "NoStorage": no storage
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- "Store": store data without error model
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- "ErrorModel": store data with error model [6]
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- **Trace setups**
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- *id* (string)
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- Trace setup id. Two files are generated by DRAMSys: an SQLite database
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file (.tdb) and a text file (.txt) containing the program output. The
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name of these files comes from this field.
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- *clkMhz*
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- Speed of the trace player
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- *bl*
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- Burst length
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- *trace file*
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- A pre-recorded file containing memory transactions to be executed by a
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trace player.
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Some attributes are self-explanatory while others require some previous
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knowhow of memory technologies or some knowledge of the simulator source code.
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Resources of the simulator are available in the **resources** directory its
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sub-directories.
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``` bash
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$ cd /projects/dram.vp.system/dram/resources
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```
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A description of the content each directory follows.
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- **resources**
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- **configs**: XML files used for configure specific details of the simulation.
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- am_configs: address mapping configuration
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- memconfigs: memory configuration
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- memspecs: configuration related to the memory technology
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- **scripts**: useful tools like address scrambler, trace analyser, database
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creator, etc.
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- **simulations**: global configuration
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- **traces**: trace files for simulations. They contain accesses to memory
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in certain known scenarios.
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#### References
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[1] TLM Modelling of 3D Stacked Wide I/O DRAM Subsystems, A Virtual Platform for Memory Controller Design Space Exploration
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M. Jung, C. Weis, N. Wehn, K. Chandrasekar. International Conference on High-Performance and Embedded Architectures and Compilers 2013 (HiPEAC), Workshop on: Rapid Simulation and Performance Evaluation: Methods and Tools (RAPIDO), January, 2013, Berlin.
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[2] DRAMPower: Open-source DRAM Power & Energy Estimation Tool
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Karthik Chandrasekar, Christian Weis, Yonghui Li, Sven Goossens, Matthias Jung, Omar Naji, Benny Akesson, Norbert Wehn, and Kees Goossens
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URL: http://www.drampower.info
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[3] Energy Optimization in 3D MPSoCs with Wide-I/O DRAM
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M. Sadri, M. Jung, C. Weis, N. Wehn, L. Benini. Conference Design, Automation and Test in Europe (DATE), March, 2014, Dresden, Germany.
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[4] DRAMSys: A flexible DRAM Subsystem Design Space Exploration Framework
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M. Jung, C. Weis, N. Wehn. Accepted for publication, IPSJ Transactions on System LSI Design Methodology (T-SLDM), October, 2015.
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[5] Optimized Active and Power-Down Mode Refresh Control in 3D-DRAMs
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M. Jung, M. Sadri, C. Weis, N. Wehn, L. Benini., VLSI-SoC, October, 2014, Playa del Carmen, Mexico.
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[6] Retention Time Measurements and Modelling of Bit Error Rates of WIDE-I/O DRAM in MPSoCs
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C. Weis, M. Jung, P. Ehses, C. Santos, P. Vivet, S. Goossens, M. Koedam, N. Wehn. Accepted for publication, IEEE Conference Design, Automation and Test in Europe (DATE), March, 2015, Grenoble, France
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[7] http://www.uni-kl.de/3d-dram/publications/
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