Derek Christ
1ef2b3bd9c
Update the DRAMUtils version and fix all configs that now require DBI parameters for the memimpedance spec.
227 lines
6.3 KiB
JSON
227 lines
6.3 KiB
JSON
{
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"simulation": {
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"addressmapping": {
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"BANKGROUP_BIT": [
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28,
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29
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],
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"BANK_BIT": [
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30,
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31
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],
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"BYTE_BIT": [
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0,
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1,
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2
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],
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"COLUMN_BIT": [
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3,
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4,
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5,
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6,
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7,
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8,
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9,
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10,
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11,
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12
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],
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"ROW_BIT": [
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13,
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14,
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15,
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16,
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17,
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18,
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19,
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20,
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21,
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22,
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23,
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24,
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25,
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26,
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27
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]
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},
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"mcconfig": {
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"Arbiter": "Simple",
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"CmdMux": "Oldest",
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"MaxActiveTransactions": 128,
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"PagePolicy": "Open",
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"PowerDownPolicy": "NoPowerDown",
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"RefreshManagement": false,
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"RefreshMaxPostponed": 0,
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"RefreshMaxPulledin": 0,
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"RefreshPolicy": "AllBank",
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"RequestBufferSize": 8,
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"RespQueue": "Fifo",
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"Scheduler": "FrFcfs",
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"SchedulerBuffer": "Bankwise"
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},
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"memspec": {
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"memarchitecturespec": {
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"burstLength": 8,
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"dataRate": 2,
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"nbrOfBankGroups": 4,
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"nbrOfBanks": 16,
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"nbrOfColumns": 1024,
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"nbrOfRanks": 1,
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"nbrOfRows": 32768,
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"width": 8,
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"nbrOfDevices": 8,
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"nbrOfChannels": 1,
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"RefMode": 1,
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"maxBurstLength": 8
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},
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"memoryId": "MICRON_4Gb_DDR4-1866_8bit_A",
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"memoryType": "DDR4",
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"mempowerspec": {
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"vdd": 1.2,
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"idd0": 56.25e-3,
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"idd2n": 33.75e-3,
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"idd3n": 39.5e-3,
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"idd4r": 157.5e-3,
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"idd4w": 135.0e-3,
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"idd6n": 20.25e-3,
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"idd2p": 17.0e-3,
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"idd3p": 22.5e-3,
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"vpp": 2.5,
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"ipp0": 4.05e-3,
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"ipp2n": 0,
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"ipp3n": 0,
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"ipp4r": 0,
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"ipp4w": 0,
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"ipp6n": 2.6e-3,
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"ipp2p": 17.0e-3,
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"ipp3p": 22.5e-3,
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"idd5B": 118.0e-3,
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"ipp5B": 0.0,
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"idd5F2": 0.0,
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"ipp5F2": 0.0,
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"idd5F4": 0.0,
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"ipp5F4": 0.0,
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"vddq": 0.0,
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"iBeta_vdd": 56.25e-3,
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"iBeta_vpp": 4.05e-3
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},
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"memtimingspec": {
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"AL": 0,
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"CCD_L": 5,
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"CCD_S": 4,
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"CKE": 6,
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"CKESR": 7,
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"CL": 13,
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"DQSCK": 2,
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"FAW": 22,
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"RAS": 32,
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"RC": 45,
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"RCD": 13,
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"REFM": 1,
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"REFI": 3644,
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"RFC1": 243,
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"RFC2": 0,
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"RFC4": 0,
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"RL": 13,
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"RPRE": 1,
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"RP": 13,
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"RRD_L": 5,
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"RRD_S": 4,
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"RTP": 8,
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"WL": 12,
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"WPRE": 1,
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"WR": 14,
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"WTR_L": 7,
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"WTR_S": 3,
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"XP": 8,
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"XPDLL": 255,
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"XS": 252,
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"XSDLL": 512,
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"ACTPDEN": 1,
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"PRPDEN": 1,
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"REFPDEN": 1,
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"RTRS": 1,
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"tCK": 1072e-12
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},
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"bankwisespec": {
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"factRho": 1.0
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},
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"memimpedancespec": {
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"ck_termination": true,
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"ck_R_eq": 1e6,
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"ck_dyn_E": 1e-12,
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"ca_termination": true,
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"ca_R_eq": 1e6,
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"ca_dyn_E": 1e-12,
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"rdq_termination": true,
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"rdq_R_eq": 1e6,
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"rdq_dyn_E": 1e-12,
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"wdq_termination": true,
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"wdq_R_eq": 1e6,
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"wdq_dyn_E": 1e-12,
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"wdqs_termination": true,
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"wdqs_R_eq": 1e6,
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"wdqs_dyn_E": 1e-12,
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"rdqs_termination": true,
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"rdqs_R_eq": 1e6,
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"rdqs_dyn_E": 1e-12,
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"rdbi_termination": true,
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"rdbi_R_eq": 1e6,
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"rdbi_dyn_E": 1e-12,
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"wdbi_termination": true,
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"wdbi_R_eq": 1e6,
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"wdbi_dyn_E": 1e-12
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},
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"prepostamble": {
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"read_zeroes": 0.0,
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"write_zeroes": 0.0,
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"read_ones": 0.0,
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"write_ones": 0.0,
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"read_zeroes_to_ones": 0,
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"write_zeroes_to_ones": 0,
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"write_ones_to_zeroes": 0,
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"read_ones_to_zeroes": 0,
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"readMinTccd": 0,
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"writeMinTccd": 0
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}
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},
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"simconfig": {
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"AddressOffset": 0,
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"CheckTLM2Protocol": false,
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"DatabaseRecording": true,
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"Debug": false,
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"EnableWindowing": false,
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"PowerAnalysis": true,
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"SimulationName": "example",
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"SimulationProgressBar": true,
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"StoreMode": "NoStorage",
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"UseMalloc": false,
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"WindowSize": 1000,
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"TogglingRate": {
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"togglingRateRead": 0.5,
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"togglingRateWrite": 0.5,
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"dutyCycleRead": 0.5,
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"dutyCycleWrite": 0.5,
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"idlePatternRead": "L",
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"idlePatternWrite": "L"
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}
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},
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"simulationid": "ddr4-example",
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"tracesetup": [
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{
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"type": "player",
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"clkMhz": 200,
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"dataLength": 64,
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"name": "traces/example.stl"
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}
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]
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}
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} |