{
    "simulation": {
        "addressmapping": {
            "BANKGROUP_BIT": [
                28,
                29
            ],
            "BANK_BIT": [
                30,
                31
            ],
            "BYTE_BIT": [
                0,
                1,
                2
            ],
            "COLUMN_BIT": [
                3,
                4,
                5,
                6,
                7,
                8,
                9,
                10,
                11,
                12
            ],
            "ROW_BIT": [
                13,
                14,
                15,
                16,
                17,
                18,
                19,
                20,
                21,
                22,
                23,
                24,
                25,
                26,
                27
            ]
        },
        "mcconfig": {
            "Arbiter": "Simple",
            "CmdMux": "Oldest",
            "MaxActiveTransactions": 128,
            "PagePolicy": "Open",
            "PowerDownPolicy": "NoPowerDown",
            "RefreshManagement": false,
            "RefreshMaxPostponed": 0,
            "RefreshMaxPulledin": 0,
            "RefreshPolicy": "AllBank",
            "RequestBufferSize": 8,
            "RespQueue": "Fifo",
            "Scheduler": "FrFcfs",
            "SchedulerBuffer": "Bankwise"
        },
        "memspec": {
            "memarchitecturespec": {
                "burstLength": 8,
                "dataRate": 2,
                "nbrOfBankGroups": 4,
                "nbrOfBanks": 16,
                "nbrOfColumns": 1024,
                "nbrOfRanks": 1,
                "nbrOfRows": 32768,
                "width": 8,
                "nbrOfDevices": 8,
                "nbrOfChannels": 1,
                "RefMode": 1,
                "maxBurstLength": 8
            },
            "memoryId": "MICRON_4Gb_DDR4-1866_8bit_A",
            "memoryType": "DDR4",
            "mempowerspec": {
                "vdd": 1.2,
                "idd0": 56.25e-3,
                "idd2n": 33.75e-3,
                "idd3n": 39.5e-3,
                "idd4r": 157.5e-3,
                "idd4w": 135.0e-3,
                "idd6n": 20.25e-3,
                "idd2p": 17.0e-3,
                "idd3p": 22.5e-3,
                
                "vpp": 2.5,
                "ipp0": 4.05e-3,
                "ipp2n": 0,
                "ipp3n": 0,
                "ipp4r": 0,
                "ipp4w": 0,
                "ipp6n": 2.6e-3,
                "ipp2p": 17.0e-3,
                "ipp3p": 22.5e-3,
                
                "idd5B": 118.0e-3,
                "ipp5B": 0.0,
                "idd5F2": 0.0,
                "ipp5F2": 0.0,
                "idd5F4": 0.0,
                "ipp5F4": 0.0,
                "vddq": 0.0,
    
                "iBeta_vdd": 56.25e-3,
                "iBeta_vpp": 4.05e-3
    
            },
            "memtimingspec": {
                "AL": 0,
                "CCD_L": 5,
                "CCD_S": 4,
                "CKE": 6,
                "CKESR": 7,
                "CL": 13,
                "DQSCK": 2,
                "FAW": 22,
                "RAS": 32,
                "RC": 45,
                "RCD": 13,
                "REFM": 1,
                "REFI": 3644,
                "RFC1": 243,
                "RFC2": 0,
                "RFC4": 0,
                "RL": 13,
                "RPRE": 1,
                "RP": 13,
                "RRD_L": 5,
                "RRD_S": 4,
                "RTP": 8,
                "WL": 12,
                "WPRE": 1,
                "WR": 14,
                "WTR_L": 7,
                "WTR_S": 3,
                "XP": 8,
                "XPDLL": 255,
                "XS": 252,
                "XSDLL": 512,
                "ACTPDEN": 1,
                "PRPDEN": 1,
                "REFPDEN": 1,
                "RTRS": 1,
                "tCK": 1072e-12
            },
            "bankwisespec": {
                "factRho": 1.0
            },
            "memimpedancespec": {
                "ck_termination": true,
                "ck_R_eq": 1e6,
                "ck_dyn_E": 1e-12,
          
                "ca_termination": true,
                "ca_R_eq": 1e6,
                "ca_dyn_E": 1e-12,
          
                "rdq_termination": true,
                "rdq_R_eq": 1e6,
                "rdq_dyn_E": 1e-12,
                "wdq_termination": true,
                "wdq_R_eq": 1e6,
                "wdq_dyn_E": 1e-12,
          
                "wdqs_termination": true,
                "wdqs_R_eq": 1e6,
                "wdqs_dyn_E": 1e-12,
                "rdqs_termination": true,
                "rdqs_R_eq": 1e6,
                "rdqs_dyn_E": 1e-12,

                "rdbi_termination": true,
                "rdbi_R_eq": 1e6,
                "rdbi_dyn_E": 1e-12,
                "wdbi_termination": true,
                "wdbi_R_eq": 1e6,
                "wdbi_dyn_E": 1e-12
            },
            "prepostamble": {
                "read_zeroes": 0.0,
                "write_zeroes": 0.0,
                "read_ones": 0.0,
                "write_ones": 0.0,
                "read_zeroes_to_ones": 0,
                "write_zeroes_to_ones": 0,
                "write_ones_to_zeroes": 0,
                "read_ones_to_zeroes": 0,
                "readMinTccd": 0,
                "writeMinTccd": 0
            }
        },
        "simconfig": {
            "AddressOffset": 0,
            "CheckTLM2Protocol": false,
            "DatabaseRecording": true,
            "Debug": false,
            "EnableWindowing": false,
            "PowerAnalysis": true,
            "SimulationName": "example",
            "SimulationProgressBar": true,
            "StoreMode": "NoStorage",
            "UseMalloc": false,
            "WindowSize": 1000,
            "TogglingRate": {
                "togglingRateRead": 0.5,
                "togglingRateWrite": 0.5,
                "dutyCycleRead": 0.5,
                "dutyCycleWrite": 0.5,
                "idlePatternRead": "L",
                "idlePatternWrite": "L"
            }
        },
        "simulationid": "ddr4-example",
        "tracesetup": [
            {
                "type": "player",
                "clkMhz": 200,
                "dataLength": 64,
                "name": "traces/example.stl"
            }
        ]
    }
}