Commit Graph

15 Commits

Author SHA1 Message Date
Éder Ferreira Zulian
76757e0025 Little clean up (as suggested in the code). 2015-05-21 17:06:24 +02:00
Éder Ferreira Zulian
6f8653e699 License header added to files. 2015-05-13 12:26:21 +02:00
Éder Ferreira Zulian
9846a56da4 Some names slightly changed to better describe their purpose.
ChipSeed --> ErrorChipSeed
csvfile --> ErrorCSVFile
StorMo --> ErrorStoreMode
StorMode --> ErrorStoreMode
StorageMode --> ErrorStorageMode

(Changes after code review)
2015-05-11 14:08:39 +02:00
Éder Ferreira Zulian
0fc640ad0d Enum class <-> string macro improved.
The macro generates code for two functions: EnumToString() and StringToEnum().

Notes:
1. this macro creates a scoped enumeration (enum class) which favors code
readability;

2. this implementation does not support assignment of values to enumerators
and also does not support multiple enumerators with the same value. The first
enumerator value is 0, the next is 1, and so on. Nevertheless, it is still
useful for many cases;

3. if an invalid string is passed to StringToEnum() the program will be
aborted and an error message describing the error will be displayed in the
standard output.
2015-05-11 12:46:21 +02:00
Éder Ferreira Zulian
19d682c0ca Typo fixed (PowerAnalysys --> PowerAnalysis) 2015-05-08 14:04:59 +02:00
Éder Ferreira Zulian
cd8aeebe6f Created an enumeration to the possible values of storage mode. 2015-05-08 12:52:49 +02:00
Matthias Jung
0f8ad59a1e Merge branch 'master' of https://git.rhrk.uni-kl.de/ehses/dram.vp.system into ehses-master
Conflicts:
	dram/dramSys/dramSys.pro
2015-04-09 10:32:06 +02:00
gernhard2
f11adf51dc Relocated the python scripts. They now live in the analyzer directory and are deployed to the output folder when building the analyzer.
Major change to simulation logic in dramSys: Commands in a transaction are now scheduled one at a time, instead of
scheduling a whole transaction at once. Since single commands (e.g. Pre or Act) are not that long, refreshes are allowed to be delayed
to allow a command to finsh. Consequently, the whole loop in the ControllerCore about trying to scheduleding a transaction and aborting it when
it collides with a refresh could be ommitted. Lastly, Fifo_Strict has been added, which is a Fifo Scheduler that forces the read and write transactions, even
between different banks to be executed in order. Fifo and FR_FCFS have been modified to fit into the new scheduling logic.
2015-02-16 08:21:27 +01:00
Peter Ehses
e84a3cc99b Merge branch 'master' of https://git.rhrk.uni-kl.de/ehses/dram.vp.system
Conflicts:
	dram/dramSys/dramSys.pro
	dram/resources/configs/amconfigs/am_wideio.xml
	dram/resources/configs/memconfigs/fr_fcfs.xml
	dram/src/common/xmlAddressdecoder.cpp
	dram/src/controller/core/configuration/ConfigurationLoader.cpp
	dram/src/simulation/Simulation.cpp
	dram/src/simulation/Simulation.h
	dram/src/simulation/TracePlayer.h
2014-12-02 15:25:48 +01:00
Janik Schlemminger
2aa07bbbe6 Quick and Dirty XML - Refactoring necessary 2014-09-04 23:35:54 +02:00
Janik Schlemminger
320331164b xml extended, sim config introduced 2014-09-03 18:52:32 +02:00
Janik Schlemminger
85a574fd5b Configuration refactoring 2014-08-30 19:22:48 +02:00
Janik Schlemminger
df6637b114 splitting config and memspec 2014-08-29 10:25:32 +02:00
Janik Schlemminger
efc6094c13 memspec class 2014-08-27 09:43:42 +02:00
robert
c5512389da changed project structure to qtcreator, added timed out powerdown 2014-05-07 17:22:20 +02:00