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Author SHA1 Message Date
Éder F. Zulian
65e52d0e75 DRAMSys and IceWrapper projects integrated. 2015-09-24 17:39:37 +02:00
Éder F. Zulian
ef975f52ea Added dram.vp.icewrapper as a submodule 2015-09-23 15:55:56 +02:00
Matthias Jung
55a9acb1aa Repaired powerdown after Refresh, however the DRAM should be awake again 
for the interval... I think this commit will break the nightly test so I
will fix that soon.
 2015-09-17 16:21:10 +02:00
Matthias Jung
b225bd6367 tests: a PRE_ALL is allowed to follow a PRE 2015-09-16 17:26:44 +02:00
Matthias Jung
5e540c5de2 fixed a lot of bugs in the tests again 2015-09-16 17:01:34 +02:00
Matthias Jung
825064c5fb Merge branch 'master' of git.rhrk.uni-kl.de:EIT-Wehn/dram.vp.system 2015-09-16 14:20:32 +02:00
Matthias Jung
d73e667bd5 Merge pull request #38 from fzeder/master 
Removal of unnecessary debug message
 2015-09-16 13:43:00 +02:00
Matthias Jung
9f8627be77 trace analyzer repaired 2015-09-16 13:34:02 +02:00
Éder F. Zulian
ec717ef8d1 Removal of unnecessary debug message 2015-09-16 11:42:34 +02:00
Matthias Jung
d84c0cd6bd Merge pull request #37 from fzeder/master 
Now it is possible to disable refreshes from config.
 2015-09-15 15:03:47 +02:00
Éder F. Zulian
2ad738c514 Now it is possible to disable refreshes from config. 2015-09-15 14:58:11 +02:00
Matthias Jung
7bfeac429b Merge branch 'master' of git.rhrk.uni-kl.de:EIT-Wehn/dram.vp.system 2015-09-14 09:53:12 +02:00
Matthias Jung
ef1fe83bb4 Added DDR3 to the config 2015-09-14 09:52:49 +02:00
Matthias Jung
4c9dfe680d added some die statements 2015-09-12 20:57:39 +02:00
Matthias Jung
01a9ec9fc4 Merge pull request #34 from fzeder/master 
Please see the individual commits.
 2015-09-08 21:53:40 +02:00
Éder F. Zulian
dfdb3791bb Using {} instead of "continue" 2015-09-08 18:01:32 +02:00
Éder F. Zulian
929239ace5 Added timestamp and duration for every test step. 2015-09-08 14:34:14 +02:00
Éder F. Zulian
d19d2425dc If the row has never been accessed (written, refreshed) do not flip bits. 2015-09-08 14:33:39 +02:00
Matthias Jung
851f487924 Merge pull request #33 from fzeder/master 
Error model automatic test is now ready to run.
 2015-09-08 10:46:03 +02:00
Éder F. Zulian
54a0a27f30 Error model automatic test is now ready to run. 2015-09-08 10:32:36 +02:00
Matthias Jung
6149981b9c Marked start.pl as executable 2015-08-06 17:00:55 +02:00
Matthias Jung
2b522c5bb4 return statement added for trace analyser 2015-08-06 17:00:38 +02:00
Matthias Jung
f4fd3b55c9 error fixed 2015-08-06 16:51:37 +02:00
Matthias Jung
424c2c771c Simple test system started. To test it just run the following: 
cd tests
        perl start.pl

Then wait until you hopefully see the result of the first test!
 2015-08-06 16:00:10 +02:00
Matthias Jung
fa006cee5f Merge pull request #28 from fzeder/master 
Directory structure changed: dramSys --> simulator
 2015-08-06 14:20:22 +02:00
Éder Ferreira Zulian
b6f9fe1cf7 Using "NoStorage" as default configuration. 2015-08-06 12:14:26 +02:00
Éder Ferreira Zulian
3515167b2b "dramSys" replaced by "simulator". 2015-08-06 11:58:22 +02:00
Éder Ferreira Zulian
905661ca6f Moving files from dramSys to simulator directory. 2015-08-06 11:03:35 +02:00
Éder Ferreira Zulian
037b2eff99 Merge remote branch 'upstream/master' 
Conflicts:
	DRAMSys/simulator/src/error/error_new.csv
	DRAMSys/simulator/src/error/flip_memory.cpp
	DRAMSys/simulator/src/error/flip_memory.h
	DRAMSys/simulator/src/error/nest_map.cpp
	DRAMSys/simulator/src/error/nest_map.h
	DRAMSys/simulator/src/simulation/Dram.h
 2015-08-06 10:52:45 +02:00
Matthias Jung
411e8bace8 Merge pull request #27 from EIT-Wehn/new-error 
New Retention Error Model
 2015-08-05 21:44:02 +02:00
Matthias Jung
339a41432d value in generator script changed 2015-08-05 21:36:24 +02:00
Matthias Jung
635b931f2f Add test setup files for the error model 2015-08-05 09:41:20 +02:00
Matthias Jung
af8624c9e9 STL data player added 2015-08-05 09:40:48 +02:00
Matthias Jung
5ba493cb70 polish 2015-08-05 09:20:22 +02:00
Matthias Jung
dbf3f71589 Polished error model 2015-08-05 09:16:31 +02:00
Matthias Jung
8be4d8077c Added function to Debug Manager that also outputs if debug is set to 0 2015-08-05 09:13:58 +02:00
Matthias Jung
d1a7ceb82f corrected name of error file in frfcfs config 2015-08-02 13:51:59 +02:00
Matthias Jung
8aae7fbed3 each bank has its own error model 2015-08-02 13:51:29 +02:00
Matthias Jung
033bffb3ff Old error model removed 2015-08-01 15:59:16 +02:00
Matthias Jung
33d88006c8 New error model finished (Testing still required) 2015-08-01 15:53:48 +02:00
Matthias Jung
ea0e628eef Added traceplayer that also reads data from the trace 2015-08-01 15:53:10 +02:00
Matthias Jung
49cc8d688e error file adjusted 2015-08-01 12:12:25 +02:00
Matthias Jung
e6051ac967 Bit flipping for independent cells is now implemented 2015-08-01 11:17:30 +02:00
Matthias Jung
91e6ecd714 Almost everyhing is integrated now: 
* File Parsing
  * Initialisation
  * Load
  * Store

The only thing that is missing is the bit flip procedure in an
activate/refresh.
 2015-07-31 23:34:29 +02:00
Matthias Jung
8fa9083676 added values for 64ms 2015-07-31 23:33:43 +02:00
Éder Ferreira Zulian
931afaf115 Target (output binary file) set back to "dramSys". 2015-07-30 13:17:49 +02:00
Éder Ferreira Zulian
4bad797949 Submodules properly moved 2015-07-30 12:31:06 +02:00
Éder Ferreira Zulian
bce738a1e0 Directory structure changed: dramSys --> simulator 2015-07-30 12:10:17 +02:00
Matthias Jung
aedf2ebeb1 addded parsing routine for the error file 2015-07-30 11:18:22 +02:00
Matthias Jung
4a60423e00 path to the error file adjusted 2015-07-30 11:17:51 +02:00