Merge pull request #37 from fzeder/master

Now it is possible to disable refreshes from config.

DRAMSys/simulator/resources/simulations/sim-batch.xml

@@ -5,6 +5,7 @@
         <PowerAnalysis value="1" />
         <NumberOfTracePlayers value="4"/>
         <NumberOfMemChannels value="4"/>
+        <ControllerCoreDisableRefresh value="0"/>
     </simconfig>
 
     <memspecs>

DRAMSys/simulator/src/controller/core/ControllerCore.cpp

@@ -123,16 +123,19 @@ ControllerCore::~ControllerCore()
 
 void ControllerCore::triggerRefresh(tlm::tlm_generic_payload& payload)
 {
-    sc_time time = sc_time_stamp();
-    Bank bank = DramExtension::getExtension(payload).getBank();
+    /* Refresh can be disabled for tests purpose */
+    if (config.ControllerCoreDisableRefresh == false) {
+        sc_time time = sc_time_stamp();
+        Bank bank = DramExtension::getExtension(payload).getBank();
 
-    state.cleanUp(time);
+        state.cleanUp(time);
 
-    if (!refreshManager->isInvalidated(payload, time) && !powerDownManager->isInSelfRefresh(bank))
-    {
-        printDebugMessage("Triggering refresh on bank " + to_string(bank.ID()));
-        powerDownManager->wakeUpForRefresh(bank, time); //expects PDNA and PDNP to exit without delay
-        refreshManager->scheduleRefresh(payload, time);
+        if (!refreshManager->isInvalidated(payload, time) && !powerDownManager->isInSelfRefresh(bank))
+        {
+            printDebugMessage("Triggering refresh on bank " + to_string(bank.ID()));
+            powerDownManager->wakeUpForRefresh(bank, time); //expects PDNA and PDNP to exit without delay
+            refreshManager->scheduleRefresh(payload, time);
+        }
     }
 }
 

DRAMSys/simulator/src/controller/core/configuration/Configuration.cpp

@@ -121,6 +121,8 @@ void Configuration::setParameter(std::string name, std::string value)
         NumberOfTracePlayers = string2int(value);
     else if (name == "NumberOfMemChannels")
         NumberOfMemChannels = string2int(value);
+    else if (name == "ControllerCoreDisableRefresh")
+        ControllerCoreDisableRefresh = string2bool(value);
     // Specification for ErrorChipSeed, ErrorCSVFile path and ErrorStoreMode
     else if(name == "ErrorChipSeed")
         ErrorChipSeed = string2int(value);

DRAMSys/simulator/src/controller/core/configuration/Configuration.h

@@ -77,6 +77,7 @@ struct Configuration
     bool Debug = false;
     unsigned int NumberOfTracePlayers = 1;
     unsigned int NumberOfMemChannels = 1;
+    bool ControllerCoreDisableRefresh = false;
 
     //MemSpec(from DRAM-Power XML)
     MemSpec memSpec;

README.md

@@ -130,6 +130,7 @@ The XML code below shows a typic configuration:
         <PowerAnalysis value="1"/>
         <NumberOfTracePlayers value="5"/>
         <NumberOfMemChannels value="1"/>
+        <ControllerCoreDisableRefresh value="0"/>
     </simconfig>
 
     <!-- Memory Specifications -->
@@ -226,6 +227,9 @@ Below are listed the configuration sections and configuration fields.
     - Number of trace players
   - *NumberOfMemChannels* (unsigned int)
     - Number of memory channels
+  - *ControllerCoreDisableRefresh* (boolean)
+    - "1": disables refreshes
+    - "0": normal operation (refreshes enabled)
 
 - **Memory specification**