Éder Ferreira Zulian
0edd064ee5
Janik Schlemminger and Robert Gernhardt added as authors.
...
Matthias Jung, Janik Schlemminger and Robert Gernhardt were used as authors
for all files which did not have an author/header.
2015-05-18 12:06:58 +02:00
Éder Ferreira Zulian
6f8653e699
License header added to files.
2015-05-13 12:26:21 +02:00
Matthias Jung
0f8ad59a1e
Merge branch 'master' of https://git.rhrk.uni-kl.de/ehses/dram.vp.system into ehses-master
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Conflicts:
dram/dramSys/dramSys.pro
2015-04-09 10:32:06 +02:00
gernhard2
f11adf51dc
Relocated the python scripts. They now live in the analyzer directory and are deployed to the output folder when building the analyzer.
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Major change to simulation logic in dramSys: Commands in a transaction are now scheduled one at a time, instead of
scheduling a whole transaction at once. Since single commands (e.g. Pre or Act) are not that long, refreshes are allowed to be delayed
to allow a command to finsh. Consequently, the whole loop in the ControllerCore about trying to scheduleding a transaction and aborting it when
it collides with a refresh could be ommitted. Lastly, Fifo_Strict has been added, which is a Fifo Scheduler that forces the read and write transactions, even
between different banks to be executed in order. Fifo and FR_FCFS have been modified to fit into the new scheduling logic.
2015-02-16 08:21:27 +01:00
Peter Ehses
e84a3cc99b
Merge branch 'master' of https://git.rhrk.uni-kl.de/ehses/dram.vp.system
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Conflicts:
dram/dramSys/dramSys.pro
dram/resources/configs/amconfigs/am_wideio.xml
dram/resources/configs/memconfigs/fr_fcfs.xml
dram/src/common/xmlAddressdecoder.cpp
dram/src/controller/core/configuration/ConfigurationLoader.cpp
dram/src/simulation/Simulation.cpp
dram/src/simulation/Simulation.h
dram/src/simulation/TracePlayer.h
2014-12-02 15:25:48 +01:00
Peter Ehses
905e75ca32
included errormodel which is presented in DATE paper
2014-12-02 14:44:46 +01:00
Janik Schlemminger
e105d54045
added fix for bankgroups and ranks in addressdecoder
2014-09-10 16:10:07 +02:00
Janik Schlemminger
938dbb3fdb
print mapping
2014-09-06 20:21:43 +02:00
Janik Schlemminger
2aa07bbbe6
Quick and Dirty XML - Refactoring necessary
2014-09-04 23:35:54 +02:00
Janik Schlemminger
8722808a90
made traceplayer generic, so that different kind of traceplayers are supported
2014-09-03 10:27:04 +02:00
Janik Schlemminger
c028314b02
bankgroup integration. act map stores scheduled command instead of bank now
2014-07-18 13:19:15 +02:00
Janik Schlemminger
dc9d1b4b1f
address decoder simplified
2014-07-15 14:35:13 +02:00
robert
c5512389da
changed project structure to qtcreator, added timed out powerdown
2014-05-07 17:22:20 +02:00
robert
b75366edda
addressmapping for ddr4
2014-04-20 22:16:32 +02:00
robert
f4af60b709
reeintegrated dram
2014-04-12 20:44:25 +02:00
robert
e547991e4e
reeintegrated dram module
2014-04-12 12:05:04 +02:00
Janik Schlemminger
a1444a4d7b
PowerDownChecker and release build setting added
2014-04-12 11:44:27 +02:00
robert
c1841e4102
corrected checkers for non-interleaving reads/writes. Added burst length to db. Added burst functionally to players
2014-04-07 20:07:44 +02:00
robert
04e38d6663
tracerecorder, refresh and stuff
2014-03-29 00:26:21 +01:00
Janik Schlemminger
cd556eb572
merged everythin into one project
2014-03-21 13:46:38 +01:00
