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README.md

@@ -1,6 +1,6 @@
-<img src="DRAMSys/docs/images/dramsys4_0.png" width="350" style="float: left;"/>  
+<img src="docs/images/dramsys_logo.png" width="350" style="float: left;" alt="DRAMSys Logo"/>  
 
-**DRAMSys4.0** is a flexible DRAM subsystem design space exploration framework based on SystemC TLM-2.0. It was developed at the [Microelectronic Systems Design Research Group](https://ems.eit.uni-kl.de/en/start/) and [Fraunhofer IESE](https://www.iese.fraunhofer.de/en.html).
+**DRAMSys** is a flexible DRAM subsystem design space exploration framework based on SystemC TLM-2.0. It was developed at the [Microelectronic Systems Design Research Group](https://ems.eit.uni-kl.de/en/start/) and [Fraunhofer IESE](https://www.iese.fraunhofer.de/en.html).
 
 \>> [Official Website](https://www.iese.fraunhofer.de/en/innovation_trends/autonomous-systems/memtonomy/DRAMSys.html) <<
 
@@ -17,19 +17,19 @@ If you decide to use DRAMSys in your research please cite the papers [2] [3]. To
 
 ## Key Features
 
-- **standalone** simulator with trace players, **gem5**-coupled simulator and **TLM-AT-compliant library**
-- support for **DDR3/4**, **LPDDR4**, **Wide I/O 1/2**, **GDDR5/5X/6** and **HBM1/2**
-- support for **DDR5**, **LPDDR5** and **HBM3** under development (contact [Matthias Jung](mailto:matthias.jung@iese.fraunhofer.de) for more information) 
-- automatic source code generation for new JEDEC standards [3] [9] from the domain-specific language DRAMml
-- FIFO, FR-FCFS and FR-FCFS with read/write grouping scheduling policies
-- open, closed, open adaptive and closed adaptive page policy [8]
-- all-bank refresh, same-bank refresh and per-bank refresh with pulled-in and postponed refresh commands
-- staggered power down [5]
-- coupling to **DRAMPower** [4] and **3D-ICE** [8] for power and thermal simulation
+- **Standalone** simulator with trace players and traffic generators, **gem5**-coupled simulator and **TLM-AT-compliant library**
+- Support for **DDR3/4**, **LPDDR4**, **Wide I/O 1/2**, **GDDR5/5X/6** and **HBM1/2**
+- Support for **DDR5**, **LPDDR5** and **HBM3** (please contact [Matthias Jung](mailto:matthias.jung@iese.fraunhofer.de) for more information) 
+- Automatic source code generation for new JEDEC standards [3] [9] from DRAMml DSL
+- Various scheduling policies
+- Open, closed and adaptive page policies [8]
+- All-bank, same-bank, per-bank and per-2-bank refresh
+- Staggered power down [5]
+- Coupling to **DRAMPower** [4] and **3D-ICE** [8] for power and thermal simulation
 - **Trace Analyzer** for visual and metric-based result analysis
 
 ## Video
-The linked video shows the background of DRAMSys and some examples how simulations can be performed.
+The linked video shows the background of DRAMSys and some examples of how simulations can be performed.
 
 [![DRAMSys Video](https://img.youtube.com/vi/xdfaGv7MPVo/0.jpg)](https://www.youtube.com/watch?v=xdfaGv7MPVo)
 
@@ -37,7 +37,7 @@ The linked video shows the background of DRAMSys and some examples how simulatio
 
 A UML diagram of the software architecture is presented below; different component implementations are left out for simplicity. More information about the architecture and functionality can be found in the papers [1] [2] [3] and in the introduction video on [Youtube](https://www.youtube.com/watch?v=8EkC3mYWpQY).
 
-<img src="DRAMSys/docs/images/dramsys_uml.png" alt="UML"  />
+<img src="docs/images/dramsys_uml.png" alt="UML"  />
 
 ## Trace Analyzer Consulting and Custom-Tailored Modifications
 
@@ -49,7 +49,7 @@ The Trace Analyzer's main window is shown below.
 
 If you are interested in the Trace Analyzer, if you need support with the setup of DRAMSys in a virtual platform of your company, or if you require custom modifications of the simulator please contact [Matthias Jung](mailto:matthias.jung@iese.fraunhofer.de).
 
-![Trace Analyzer Main Window](DRAMSys/docs/images/traceanalyzer.png) 
+![Trace Analyzer Main Window](docs/images/traceanalyzer.png) 
 
 ## Basic Setup