From f4bc3867fc34bffadf319cc578096b41a3fb517f Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Mon, 30 Jan 2023 17:22:45 +0100 Subject: [PATCH] Add images of readme. --- .gitattributes | 1 + README.md | 28 ++++++++++++++-------------- docs/images/dramsys_logo.png | 3 +++ docs/images/dramsys_uml.png | 3 +++ docs/images/traceanalyzer.png | 3 +++ 5 files changed, 24 insertions(+), 14 deletions(-) create mode 100644 docs/images/dramsys_logo.png create mode 100644 docs/images/dramsys_uml.png create mode 100644 docs/images/traceanalyzer.png diff --git a/.gitattributes b/.gitattributes index 2ff1990f..089d44d1 100644 --- a/.gitattributes +++ b/.gitattributes @@ -2,3 +2,4 @@ *.data.gz filter=lfs diff=lfs merge=lfs -text *.inst.gz filter=lfs diff=lfs merge=lfs -text *.tdb filter=lfs diff=lfs merge=lfs -text +*.png filter=lfs diff=lfs merge=lfs -text diff --git a/README.md b/README.md index 2b81e63a..f73f0c25 100644 --- a/README.md +++ b/README.md @@ -1,6 +1,6 @@ - +DRAMSys Logo -**DRAMSys4.0** is a flexible DRAM subsystem design space exploration framework based on SystemC TLM-2.0. It was developed at the [Microelectronic Systems Design Research Group](https://ems.eit.uni-kl.de/en/start/) and [Fraunhofer IESE](https://www.iese.fraunhofer.de/en.html). +**DRAMSys** is a flexible DRAM subsystem design space exploration framework based on SystemC TLM-2.0. It was developed at the [Microelectronic Systems Design Research Group](https://ems.eit.uni-kl.de/en/start/) and [Fraunhofer IESE](https://www.iese.fraunhofer.de/en.html). \>> [Official Website](https://www.iese.fraunhofer.de/en/innovation_trends/autonomous-systems/memtonomy/DRAMSys.html) << @@ -17,19 +17,19 @@ If you decide to use DRAMSys in your research please cite the papers [2] [3]. To ## Key Features -- **standalone** simulator with trace players, **gem5**-coupled simulator and **TLM-AT-compliant library** -- support for **DDR3/4**, **LPDDR4**, **Wide I/O 1/2**, **GDDR5/5X/6** and **HBM1/2** -- support for **DDR5**, **LPDDR5** and **HBM3** under development (contact [Matthias Jung](mailto:matthias.jung@iese.fraunhofer.de) for more information) -- automatic source code generation for new JEDEC standards [3] [9] from the domain-specific language DRAMml -- FIFO, FR-FCFS and FR-FCFS with read/write grouping scheduling policies -- open, closed, open adaptive and closed adaptive page policy [8] -- all-bank refresh, same-bank refresh and per-bank refresh with pulled-in and postponed refresh commands -- staggered power down [5] -- coupling to **DRAMPower** [4] and **3D-ICE** [8] for power and thermal simulation +- **Standalone** simulator with trace players and traffic generators, **gem5**-coupled simulator and **TLM-AT-compliant library** +- Support for **DDR3/4**, **LPDDR4**, **Wide I/O 1/2**, **GDDR5/5X/6** and **HBM1/2** +- Support for **DDR5**, **LPDDR5** and **HBM3** (please contact [Matthias Jung](mailto:matthias.jung@iese.fraunhofer.de) for more information) +- Automatic source code generation for new JEDEC standards [3] [9] from DRAMml DSL +- Various scheduling policies +- Open, closed and adaptive page policies [8] +- All-bank, same-bank, per-bank and per-2-bank refresh +- Staggered power down [5] +- Coupling to **DRAMPower** [4] and **3D-ICE** [8] for power and thermal simulation - **Trace Analyzer** for visual and metric-based result analysis ## Video -The linked video shows the background of DRAMSys and some examples how simulations can be performed. +The linked video shows the background of DRAMSys and some examples of how simulations can be performed. [![DRAMSys Video](https://img.youtube.com/vi/xdfaGv7MPVo/0.jpg)](https://www.youtube.com/watch?v=xdfaGv7MPVo) @@ -37,7 +37,7 @@ The linked video shows the background of DRAMSys and some examples how simulatio A UML diagram of the software architecture is presented below; different component implementations are left out for simplicity. More information about the architecture and functionality can be found in the papers [1] [2] [3] and in the introduction video on [Youtube](https://www.youtube.com/watch?v=8EkC3mYWpQY). -UML +UML ## Trace Analyzer Consulting and Custom-Tailored Modifications @@ -49,7 +49,7 @@ The Trace Analyzer's main window is shown below. If you are interested in the Trace Analyzer, if you need support with the setup of DRAMSys in a virtual platform of your company, or if you require custom modifications of the simulator please contact [Matthias Jung](mailto:matthias.jung@iese.fraunhofer.de). -![Trace Analyzer Main Window](DRAMSys/docs/images/traceanalyzer.png) +![Trace Analyzer Main Window](docs/images/traceanalyzer.png) ## Basic Setup diff --git a/docs/images/dramsys_logo.png b/docs/images/dramsys_logo.png new file mode 100644 index 00000000..856cbde2 --- /dev/null +++ b/docs/images/dramsys_logo.png @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:74230fea7a27704772d6c519cd87a6d7f030406fdc6b0fa2a1b3ef06fddcd7b2 +size 48614 diff --git a/docs/images/dramsys_uml.png b/docs/images/dramsys_uml.png new file mode 100644 index 00000000..554a10c7 --- /dev/null +++ b/docs/images/dramsys_uml.png @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:376d0ae8425c75d974e2bfce79448bfb346d9592879e909e8a75e6eb542bf4a9 +size 237217 diff --git a/docs/images/traceanalyzer.png b/docs/images/traceanalyzer.png new file mode 100644 index 00000000..2e1affe4 --- /dev/null +++ b/docs/images/traceanalyzer.png @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:76588299b4a04c4c76ffde81994985f73c4f2b38f02d91a12e61bab8a5acb3bf +size 1686917