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Added 'bank in group' granularity for ddr5.

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This commit is contained in:
Iron Prando da Silva
2022-03-21 11:02:33 +01:00
parent c58ac6cfcc
commit f0caf8b60c
11 changed files with 73 additions and 43 deletions
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6
DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/DDR5Configuration.cpp
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@@ -44,7 +44,9 @@ DDR5Configuration::DDR5Configuration(const TraceDB& tdb) {
std::shared_ptr<DBPhaseEntryBase> DDR5Configuration::makePhaseEntry(const QSqlQuery& query) const {
auto phase = std::make_shared<DDR5DBPhaseEntry>(query);
std::dynamic_pointer_cast<TimeDependenciesInfoDDR5>(mDeviceDeps)->rankIDToRankIDs(phase->tRank, phase->tLogicalRank, phase->tPhysicalRank, phase->tDIMMRank);
auto device = std::dynamic_pointer_cast<TimeDependenciesInfoDDR5>(mDeviceDeps);
device->rankIDToRankIDs(phase->tRank, phase->tLogicalRank, phase->tPhysicalRank, phase->tDIMMRank);
device->bankIDToBankInGroup(phase->tLogicalRank, phase->tBank, phase->tBankInGroup);
return phase;
}

5
DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR5dbphaseentry.cpp
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@@ -60,6 +60,10 @@ bool DDR5DBPhaseEntry::potentialDependency(const TimeDependency& dep, const std:
dep.depType == DependencyType::IntraBankGroup
&& tBankgroup != other->tBankgroup
};
bool const skipOnIntraBankInGroupAndDifferentBankInGroup = {
dep.depType == DependencyType::IntraBankInGroup
&& tBankInGroup != other->tBankInGroup
};
bool const skipOnIntraLogRankAndDifferentRanks = {
dep.depType == DependencyType::IntraLogicalRank
&& tLogicalRank != other->tLogicalRank
@@ -81,6 +85,7 @@ bool DDR5DBPhaseEntry::potentialDependency(const TimeDependency& dep, const std:
return !(
skipOnIntraBankAndDifferentBanks
|| skipOnIntraBankgroupAndDifferentBankgroup
|| skipOnIntraBankInGroupAndDifferentBankInGroup
|| skipOnIntraLogRankAndDifferentRanks
|| skipOnIntraPhysRankAndDifferentRanks
|| skipOnIntraDIMMRankAndDifferentRanks

1
DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR5dbphaseentry.h
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@@ -42,6 +42,7 @@ class DDR5DBPhaseEntry : public DBPhaseEntryBase {
DDR5DBPhaseEntry(const QSqlQuery&);
size_t tBankgroup;
size_t tBankInGroup;
size_t tRank;
size_t tLogicalRank;

3
DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/poolcontroller.h
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@@ -46,7 +46,8 @@ public:
void push(DBDependencyEntry);
void increment();
void merge(std::vector<DBDependencyEntry>& depEntries);
size_t count() { return mCount; }
bool isDependency(const StringMapper& phaseName);
protected:

12
DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/poolcontrollermap.cpp
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@@ -83,3 +83,15 @@ bool PoolControllerMap::isDependency(const StringMapper& poolName, const StringM
}
}
size_t PoolControllerMap::count(const StringMapper& poolName) {
auto pool = mPools.find(poolName);
if (pool != mPools.end()) {
return pool->second.count();
} else {
// TODO throw?
return 0;
}
}

2
DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/poolcontrollermap.h
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@@ -46,9 +46,11 @@ public:
void push(const StringMapper& poolName, DBDependencyEntry);
void increment(const StringMapper& poolName);
void merge(std::vector<DBDependencyEntry>& depEntries);
size_t count(const StringMapper& poolName);
bool isDependency(const StringMapper& poolName, const StringMapper& phaseName);
protected:
std::map<StringMapper, PoolController> mPools;

57
DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR5.cpp
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@@ -41,26 +41,27 @@ using namespace std;
TimeDependenciesInfoDDR5::TimeDependenciesInfoDDR5(const QJsonObject& memspec, const uint tCK) : DRAMTimeDependenciesBase(memspec, tCK) {
mInitializeValues();
mBitsDIMMRanks = ceil(log2(mNumOfDIMMRanks));
mBitsPhysicalRanks = ceil(log2(mNumOfPhysicalRanks));
mBitsLogicalRanks = ceil(log2(mNumOfLogicalRanks));
mLogRankMask = (1 << mBitsLogicalRanks) - 1;
mPhysRankMask = ((1 << mBitsPhysicalRanks) - 1) << mBitsLogicalRanks;
mDIMMRankMask = ((1 << mBitsDIMMRanks) - 1) << mBitsPhysicalRanks << mBitsLogicalRanks;
}
void TimeDependenciesInfoDDR5::rankIDToRankIDs(size_t rankID, size_t& dimmRID, size_t& physRID, size_t& logRID) const {
logRID = (rankID & mLogRankMask);
physRID = (rankID & mPhysRankMask) >> mBitsLogicalRanks;
dimmRID = (rankID & mDIMMRankMask) >> mBitsPhysicalRanks >> mBitsLogicalRanks;
logRID = rankID;
physRID = logRID / mNumLogicalRanksPerPhysicalRank;
dimmRID = physRID / mNumPhysicalRanksPerDIMMRank;
}
void TimeDependenciesInfoDDR5::bankIDToBankInGroup(size_t logicalRankID, size_t bankID, size_t& bankInGroup) const {
bankInGroup = logicalRankID * mNumBanksPerGroup + bankID % mNumBanksPerGroup;
}
void TimeDependenciesInfoDDR5::mInitializeValues() {
mNumOfRanks = mMemspecJson["memarchitecturespec"].toObject()["nbrOfRanks"].toInt();
mNumOfDIMMRanks = mMemspecJson["memarchitecturespec"].toObject()["nbrOfDIMMRanks"].toInt();
mNumOfPhysicalRanks = mMemspecJson["memarchitecturespec"].toObject()["nbrOfPhysicalRanks"].toInt();
mNumOfLogicalRanks = mMemspecJson["memarchitecturespec"].toObject()["nbrOfLogicalRanks"].toInt();
mNumPhysicalRanksPerDIMMRank = mMemspecJson["memarchitecturespec"].toObject()["nbrOfPhysicalRanks"].toInt();
mNumLogicalRanksPerPhysicalRank = mMemspecJson["memarchitecturespec"].toObject()["nbrOfLogicalRanks"].toInt();
mNumBanksPerGroup = mMemspecJson["memarchitecturespec"].toObject()["nbrOfBanks"].toInt(1);
mNumBanksPerGroup /= mMemspecJson["memarchitecturespec"].toObject()["nbrOfBankGroups"].toInt(1);
burstLength = mMemspecJson["memarchitecturespec"].toObject()["burstLength"].toInt();
dataRate = mMemspecJson["memarchitecturespec"].toObject()["dataRate"].toInt();
@@ -248,14 +249,14 @@ DependencyMap TimeDependenciesInfoDDR5::mSpecializedGetDependencies() const {
{tWRAACT, "WRA", DependencyType::IntraBank, "tWRAACT"},
{tWRAACT + tBURST16, "WRA", DependencyType::IntraBank, "tWRAACT + tBURST16"},
{tRP - cmdLengthDiff, "PREPB", DependencyType::IntraBank, "tRP - tCK"},
{tRP - cmdLengthDiff, "PRESB", DependencyType::IntraBankGroup, "tRP - tCK"},
{tRP - cmdLengthDiff, "PRESB", DependencyType::IntraBankInGroup, "tRP - tCK"},
{tRP - cmdLengthDiff, "PREAB", DependencyType::IntraLogicalRank, "tRP - tCK"},
{tRFC_slr - cmdLengthDiff, "REFAB", DependencyType::IntraLogicalRank, "tRFC_slr - tCK"},
{tRFC_slr - cmdLengthDiff, "RFMAB", DependencyType::IntraLogicalRank, "tRFC_slr - tCK"},
{tRFCsb_slr - cmdLengthDiff, "REFSB", DependencyType::IntraBankGroup, "tRFCsb_slr - tCK"},
{tRFCsb_slr - cmdLengthDiff, "REFSB", DependencyType::IntraBankInGroup, "tRFCsb_slr - tCK"},
{tREFSBRD_slr - cmdLengthDiff, "REFSB", DependencyType::IntraLogicalRank, "tREFSBRD_slr - tCK"},
{tREFSBRD_dlr - cmdLengthDiff, "REFSB", DependencyType::IntraPhysicalRank, "tREFSBRD_dlr - tCK"},
{tRFCsb_slr - cmdLengthDiff, "RFMSB", DependencyType::IntraBankGroup, "tRFCsb_slr - tCK"},
{tRFCsb_slr - cmdLengthDiff, "RFMSB", DependencyType::IntraBankInGroup, "tRFCsb_slr - tCK"},
{tREFSBRD_slr - cmdLengthDiff, "RFMSB", DependencyType::IntraLogicalRank, "tREFSBRD_slr - tCK"},
{tREFSBRD_dlr - cmdLengthDiff, "RFMSB", DependencyType::IntraPhysicalRank, "tREFSBRD_dlr - tCK"},
{2 * tCK, "CMD_BUS", DependencyType::InterDIMMRank, "CommandBus"},
@@ -523,13 +524,13 @@ DependencyMap TimeDependenciesInfoDDR5::mSpecializedGetDependencies() const {
forward_as_tuple("REFSB"),
forward_as_tuple(
initializer_list<TimeDependency>{
{tRC + cmdLengthDiff, "ACT", DependencyType::IntraBankGroup, "tRC + tCK"},
{tRC + cmdLengthDiff, "ACT", DependencyType::IntraBankInGroup, "tRC + tCK"},
{tRRD_L_slr + cmdLengthDiff, "ACT", DependencyType::IntraLogicalRank, "tRRD_L_slr + tCK"},
{tRDAACT + cmdLengthDiff, "RDA", DependencyType::IntraBankGroup, "tRDAACT + tCK"},
{tWRAACT + tRP + cmdLengthDiff, "WRA", DependencyType::IntraBankGroup, "tWRAACT + tRP + tCK"},
{tWRAACT + tRP + cmdLengthDiff + tBURST16, "WRA", DependencyType::IntraBankGroup, "tWRAACT + tRP + tCK + tBURST16"},
{tRP, "PREPB", DependencyType::IntraBankGroup, "tRP"},
{tRP, "PRESB", DependencyType::IntraBankGroup, "tRP"},
{tRDAACT + cmdLengthDiff, "RDA", DependencyType::IntraBankInGroup, "tRDAACT + tCK"},
{tWRAACT + tRP + cmdLengthDiff, "WRA", DependencyType::IntraBankInGroup, "tWRAACT + tRP + tCK"},
{tWRAACT + tRP + cmdLengthDiff + tBURST16, "WRA", DependencyType::IntraBankInGroup, "tWRAACT + tRP + tCK + tBURST16"},
{tRP, "PREPB", DependencyType::IntraBankInGroup, "tRP"},
{tRP, "PRESB", DependencyType::IntraBankInGroup, "tRP"},
{tRFC_slr, "REFAB", DependencyType::IntraLogicalRank, "tRFC_slr"},
{tRFC_dlr, "REFAB", DependencyType::IntraPhysicalRank, "tRFC_dlr"},
{tRFC_dpr, "REFAB", DependencyType::IntraDIMMRank, "tRFC_dpr"},
@@ -600,13 +601,13 @@ DependencyMap TimeDependenciesInfoDDR5::mSpecializedGetDependencies() const {
forward_as_tuple("PRESB"),
forward_as_tuple(
initializer_list<TimeDependency>{
{tRAS + cmdLengthDiff, "ACT", DependencyType::IntraBankGroup, "tRAS + tCK"},
{tRTP + cmdLengthDiff, "RD", DependencyType::IntraBankGroup, "tRTP + tCK"},
{tRTP + cmdLengthDiff, "RDA", DependencyType::IntraBankGroup, "tRTP + tCK"},
{tWRPRE + cmdLengthDiff, "WR", DependencyType::IntraBankGroup, "tWRPRE + tCK"},
{tWRPRE + cmdLengthDiff + tBURST16, "WR", DependencyType::IntraBankGroup, "tWRPRE + tCK + tBURST16"},
{tWRPRE + cmdLengthDiff, "WRA", DependencyType::IntraBankGroup, "tWRPRE + tCK"},
{tWRPRE + cmdLengthDiff + tBURST16, "WRA", DependencyType::IntraBankGroup, "tWRPRE + tCK + tBURST16"},
{tRAS + cmdLengthDiff, "ACT", DependencyType::IntraBankInGroup, "tRAS + tCK"},
{tRTP + cmdLengthDiff, "RD", DependencyType::IntraBankInGroup, "tRTP + tCK"},
{tRTP + cmdLengthDiff, "RDA", DependencyType::IntraBankInGroup, "tRTP + tCK"},
{tWRPRE + cmdLengthDiff, "WR", DependencyType::IntraBankInGroup, "tWRPRE + tCK"},
{tWRPRE + cmdLengthDiff + tBURST16, "WR", DependencyType::IntraBankInGroup, "tWRPRE + tCK + tBURST16"},
{tWRPRE + cmdLengthDiff, "WRA", DependencyType::IntraBankInGroup, "tWRPRE + tCK"},
{tWRPRE + cmdLengthDiff + tBURST16, "WRA", DependencyType::IntraBankInGroup, "tWRPRE + tCK + tBURST16"},
{tPPD, "PREPB", DependencyType::IntraPhysicalRank, "tPPD"},
{tPPD, "PREAB", DependencyType::IntraPhysicalRank, "tPPD"},
{tCK, "CMD_BUS", DependencyType::InterDIMMRank, "CommandBus"},

14
DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR5.h
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@@ -44,6 +44,7 @@ class TimeDependenciesInfoDDR5 final : public DRAMTimeDependenciesBase {
static const std::vector<QString> getPossiblePhases();
void rankIDToRankIDs(size_t rankID, size_t& dimmRID, size_t& physRID, size_t& logRID) const;
void bankIDToBankInGroup(size_t logicalRankID, size_t bankID, size_t& bankInGroup) const;
protected:
void mInitializeValues() override;
@@ -52,8 +53,9 @@ class TimeDependenciesInfoDDR5 final : public DRAMTimeDependenciesBase {
protected:
uint mNumOfRanks;
uint mNumOfDIMMRanks;
uint mNumOfPhysicalRanks;
uint mNumOfLogicalRanks;
uint mNumLogicalRanksPerPhysicalRank;
uint mNumPhysicalRanksPerDIMMRank;
uint mNumBanksPerGroup;
uint burstLength;
uint dataRate;
@@ -139,13 +141,5 @@ class TimeDependenciesInfoDDR5 final : public DRAMTimeDependenciesBase {
uint tBURST16;
uint tBURST32;
protected:
uint mBitsDIMMRanks;
uint mBitsPhysicalRanks;
uint mBitsLogicalRanks;
uint mLogRankMask;
uint mPhysRankMask;
uint mDIMMRankMask;
};

12
DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/phasedependenciestracker.cpp
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@@ -261,9 +261,17 @@ PhaseDependenciesTracker::mCalculateDependencies(const std::shared_ptr<Configura
otherPhase->id,
otherPhase->phaseName.getIDStr()
});
}
} else if (timeDiff < dep.timeValue && dep.phaseDep == StringMapper::Identifier::CMD_BUS) {
poolController.push(dep.phaseDep, DBDependencyEntry{
phase->id,
phase->phaseName.getIDStr(),
PhaseDependency::dependencyTypeName(dep.depType),
dep.timeDepName,
otherPhase->id,
otherPhase->phaseName.getIDStr()
});
if (timeDiff < dep.timeValue) {
} else if (timeDiff < dep.timeValue) {
poolController.increment(dep.phaseDep);
}

3
DRAMSys/traceAnalyzer/businessObjects/phases/phasedependency.cpp
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@@ -138,6 +138,9 @@ QString PhaseDependency::dependencyTypeName(DependencyType dtype) {
case IntraBankGroup:
return "IntraBankGroup";
case IntraBankInGroup:
return "IntraBankInGroup";
case IntraRank:
return "IntraRank";

1
DRAMSys/traceAnalyzer/businessObjects/phases/phasedependency.h
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@@ -50,6 +50,7 @@ enum DependencyType
{
IntraBank,
IntraBankGroup,
IntraBankInGroup,
IntraRank,
IntraLogicalRank,
IntraPhysicalRank,