From f0caf8b60c480c469e26806e615842ae9c982aaf Mon Sep 17 00:00:00 2001 From: Iron Prando da Silva Date: Mon, 21 Mar 2022 11:02:33 +0100 Subject: [PATCH] Added 'bank in group' granularity for ddr5. --- .../specialized/DDR5Configuration.cpp | 6 +- .../specialized/DDR5dbphaseentry.cpp | 5 ++ .../dbEntries/specialized/DDR5dbphaseentry.h | 1 + .../deviceDependencies/poolcontroller.h | 3 +- .../deviceDependencies/poolcontrollermap.cpp | 12 ++++ .../deviceDependencies/poolcontrollermap.h | 2 + .../specialized/TimeDependenciesInfoDDR5.cpp | 57 ++++++++++--------- .../specialized/TimeDependenciesInfoDDR5.h | 14 ++--- .../phasedependenciestracker.cpp | 12 +++- .../phases/phasedependency.cpp | 3 + .../businessObjects/phases/phasedependency.h | 1 + 11 files changed, 73 insertions(+), 43 deletions(-) diff --git a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/DDR5Configuration.cpp b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/DDR5Configuration.cpp index d43b27b5..e0957d53 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/DDR5Configuration.cpp +++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/DDR5Configuration.cpp @@ -44,7 +44,9 @@ DDR5Configuration::DDR5Configuration(const TraceDB& tdb) { std::shared_ptr DDR5Configuration::makePhaseEntry(const QSqlQuery& query) const { auto phase = std::make_shared(query); - std::dynamic_pointer_cast(mDeviceDeps)->rankIDToRankIDs(phase->tRank, phase->tLogicalRank, phase->tPhysicalRank, phase->tDIMMRank); - + auto device = std::dynamic_pointer_cast(mDeviceDeps); + device->rankIDToRankIDs(phase->tRank, phase->tLogicalRank, phase->tPhysicalRank, phase->tDIMMRank); + device->bankIDToBankInGroup(phase->tLogicalRank, phase->tBank, phase->tBankInGroup); + return phase; } diff --git a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR5dbphaseentry.cpp b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR5dbphaseentry.cpp index d2e95f6c..adeee0d8 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR5dbphaseentry.cpp +++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR5dbphaseentry.cpp @@ -60,6 +60,10 @@ bool DDR5DBPhaseEntry::potentialDependency(const TimeDependency& dep, const std: dep.depType == DependencyType::IntraBankGroup && tBankgroup != other->tBankgroup }; + bool const skipOnIntraBankInGroupAndDifferentBankInGroup = { + dep.depType == DependencyType::IntraBankInGroup + && tBankInGroup != other->tBankInGroup + }; bool const skipOnIntraLogRankAndDifferentRanks = { dep.depType == DependencyType::IntraLogicalRank && tLogicalRank != other->tLogicalRank @@ -81,6 +85,7 @@ bool DDR5DBPhaseEntry::potentialDependency(const TimeDependency& dep, const std: return !( skipOnIntraBankAndDifferentBanks || skipOnIntraBankgroupAndDifferentBankgroup + || skipOnIntraBankInGroupAndDifferentBankInGroup || skipOnIntraLogRankAndDifferentRanks || skipOnIntraPhysRankAndDifferentRanks || skipOnIntraDIMMRankAndDifferentRanks diff --git a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR5dbphaseentry.h b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR5dbphaseentry.h index 6b118760..cf94e903 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR5dbphaseentry.h +++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR5dbphaseentry.h @@ -42,6 +42,7 @@ class DDR5DBPhaseEntry : public DBPhaseEntryBase { DDR5DBPhaseEntry(const QSqlQuery&); size_t tBankgroup; + size_t tBankInGroup; size_t tRank; size_t tLogicalRank; diff --git a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/poolcontroller.h b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/poolcontroller.h index 17f7aefb..ac650bf9 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/poolcontroller.h +++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/poolcontroller.h @@ -46,7 +46,8 @@ public: void push(DBDependencyEntry); void increment(); void merge(std::vector& depEntries); - + size_t count() { return mCount; } + bool isDependency(const StringMapper& phaseName); protected: diff --git a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/poolcontrollermap.cpp b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/poolcontrollermap.cpp index 95ba8ebe..c20f7d18 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/poolcontrollermap.cpp +++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/poolcontrollermap.cpp @@ -83,3 +83,15 @@ bool PoolControllerMap::isDependency(const StringMapper& poolName, const StringM } } + +size_t PoolControllerMap::count(const StringMapper& poolName) { + auto pool = mPools.find(poolName); + if (pool != mPools.end()) { + return pool->second.count(); + + } else { + // TODO throw? + return 0; + + } +} diff --git a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/poolcontrollermap.h b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/poolcontrollermap.h index b7d247f1..fa5b7910 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/poolcontrollermap.h +++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/poolcontrollermap.h @@ -46,9 +46,11 @@ public: void push(const StringMapper& poolName, DBDependencyEntry); void increment(const StringMapper& poolName); void merge(std::vector& depEntries); + size_t count(const StringMapper& poolName); bool isDependency(const StringMapper& poolName, const StringMapper& phaseName); + protected: std::map mPools; diff --git a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR5.cpp b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR5.cpp index 60083362..dc087ca7 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR5.cpp +++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR5.cpp @@ -41,26 +41,27 @@ using namespace std; TimeDependenciesInfoDDR5::TimeDependenciesInfoDDR5(const QJsonObject& memspec, const uint tCK) : DRAMTimeDependenciesBase(memspec, tCK) { mInitializeValues(); - mBitsDIMMRanks = ceil(log2(mNumOfDIMMRanks)); - mBitsPhysicalRanks = ceil(log2(mNumOfPhysicalRanks)); - mBitsLogicalRanks = ceil(log2(mNumOfLogicalRanks)); - - mLogRankMask = (1 << mBitsLogicalRanks) - 1; - mPhysRankMask = ((1 << mBitsPhysicalRanks) - 1) << mBitsLogicalRanks; - mDIMMRankMask = ((1 << mBitsDIMMRanks) - 1) << mBitsPhysicalRanks << mBitsLogicalRanks; } void TimeDependenciesInfoDDR5::rankIDToRankIDs(size_t rankID, size_t& dimmRID, size_t& physRID, size_t& logRID) const { - logRID = (rankID & mLogRankMask); - physRID = (rankID & mPhysRankMask) >> mBitsLogicalRanks; - dimmRID = (rankID & mDIMMRankMask) >> mBitsPhysicalRanks >> mBitsLogicalRanks; + logRID = rankID; + physRID = logRID / mNumLogicalRanksPerPhysicalRank; + dimmRID = physRID / mNumPhysicalRanksPerDIMMRank; +} + +void TimeDependenciesInfoDDR5::bankIDToBankInGroup(size_t logicalRankID, size_t bankID, size_t& bankInGroup) const { + bankInGroup = logicalRankID * mNumBanksPerGroup + bankID % mNumBanksPerGroup; + } void TimeDependenciesInfoDDR5::mInitializeValues() { mNumOfRanks = mMemspecJson["memarchitecturespec"].toObject()["nbrOfRanks"].toInt(); mNumOfDIMMRanks = mMemspecJson["memarchitecturespec"].toObject()["nbrOfDIMMRanks"].toInt(); - mNumOfPhysicalRanks = mMemspecJson["memarchitecturespec"].toObject()["nbrOfPhysicalRanks"].toInt(); - mNumOfLogicalRanks = mMemspecJson["memarchitecturespec"].toObject()["nbrOfLogicalRanks"].toInt(); + mNumPhysicalRanksPerDIMMRank = mMemspecJson["memarchitecturespec"].toObject()["nbrOfPhysicalRanks"].toInt(); + mNumLogicalRanksPerPhysicalRank = mMemspecJson["memarchitecturespec"].toObject()["nbrOfLogicalRanks"].toInt(); + + mNumBanksPerGroup = mMemspecJson["memarchitecturespec"].toObject()["nbrOfBanks"].toInt(1); + mNumBanksPerGroup /= mMemspecJson["memarchitecturespec"].toObject()["nbrOfBankGroups"].toInt(1); burstLength = mMemspecJson["memarchitecturespec"].toObject()["burstLength"].toInt(); dataRate = mMemspecJson["memarchitecturespec"].toObject()["dataRate"].toInt(); @@ -248,14 +249,14 @@ DependencyMap TimeDependenciesInfoDDR5::mSpecializedGetDependencies() const { {tWRAACT, "WRA", DependencyType::IntraBank, "tWRAACT"}, {tWRAACT + tBURST16, "WRA", DependencyType::IntraBank, "tWRAACT + tBURST16"}, {tRP - cmdLengthDiff, "PREPB", DependencyType::IntraBank, "tRP - tCK"}, - {tRP - cmdLengthDiff, "PRESB", DependencyType::IntraBankGroup, "tRP - tCK"}, + {tRP - cmdLengthDiff, "PRESB", DependencyType::IntraBankInGroup, "tRP - tCK"}, {tRP - cmdLengthDiff, "PREAB", DependencyType::IntraLogicalRank, "tRP - tCK"}, {tRFC_slr - cmdLengthDiff, "REFAB", DependencyType::IntraLogicalRank, "tRFC_slr - tCK"}, {tRFC_slr - cmdLengthDiff, "RFMAB", DependencyType::IntraLogicalRank, "tRFC_slr - tCK"}, - {tRFCsb_slr - cmdLengthDiff, "REFSB", DependencyType::IntraBankGroup, "tRFCsb_slr - tCK"}, + {tRFCsb_slr - cmdLengthDiff, "REFSB", DependencyType::IntraBankInGroup, "tRFCsb_slr - tCK"}, {tREFSBRD_slr - cmdLengthDiff, "REFSB", DependencyType::IntraLogicalRank, "tREFSBRD_slr - tCK"}, {tREFSBRD_dlr - cmdLengthDiff, "REFSB", DependencyType::IntraPhysicalRank, "tREFSBRD_dlr - tCK"}, - {tRFCsb_slr - cmdLengthDiff, "RFMSB", DependencyType::IntraBankGroup, "tRFCsb_slr - tCK"}, + {tRFCsb_slr - cmdLengthDiff, "RFMSB", DependencyType::IntraBankInGroup, "tRFCsb_slr - tCK"}, {tREFSBRD_slr - cmdLengthDiff, "RFMSB", DependencyType::IntraLogicalRank, "tREFSBRD_slr - tCK"}, {tREFSBRD_dlr - cmdLengthDiff, "RFMSB", DependencyType::IntraPhysicalRank, "tREFSBRD_dlr - tCK"}, {2 * tCK, "CMD_BUS", DependencyType::InterDIMMRank, "CommandBus"}, @@ -523,13 +524,13 @@ DependencyMap TimeDependenciesInfoDDR5::mSpecializedGetDependencies() const { forward_as_tuple("REFSB"), forward_as_tuple( initializer_list{ - {tRC + cmdLengthDiff, "ACT", DependencyType::IntraBankGroup, "tRC + tCK"}, + {tRC + cmdLengthDiff, "ACT", DependencyType::IntraBankInGroup, "tRC + tCK"}, {tRRD_L_slr + cmdLengthDiff, "ACT", DependencyType::IntraLogicalRank, "tRRD_L_slr + tCK"}, - {tRDAACT + cmdLengthDiff, "RDA", DependencyType::IntraBankGroup, "tRDAACT + tCK"}, - {tWRAACT + tRP + cmdLengthDiff, "WRA", DependencyType::IntraBankGroup, "tWRAACT + tRP + tCK"}, - {tWRAACT + tRP + cmdLengthDiff + tBURST16, "WRA", DependencyType::IntraBankGroup, "tWRAACT + tRP + tCK + tBURST16"}, - {tRP, "PREPB", DependencyType::IntraBankGroup, "tRP"}, - {tRP, "PRESB", DependencyType::IntraBankGroup, "tRP"}, + {tRDAACT + cmdLengthDiff, "RDA", DependencyType::IntraBankInGroup, "tRDAACT + tCK"}, + {tWRAACT + tRP + cmdLengthDiff, "WRA", DependencyType::IntraBankInGroup, "tWRAACT + tRP + tCK"}, + {tWRAACT + tRP + cmdLengthDiff + tBURST16, "WRA", DependencyType::IntraBankInGroup, "tWRAACT + tRP + tCK + tBURST16"}, + {tRP, "PREPB", DependencyType::IntraBankInGroup, "tRP"}, + {tRP, "PRESB", DependencyType::IntraBankInGroup, "tRP"}, {tRFC_slr, "REFAB", DependencyType::IntraLogicalRank, "tRFC_slr"}, {tRFC_dlr, "REFAB", DependencyType::IntraPhysicalRank, "tRFC_dlr"}, {tRFC_dpr, "REFAB", DependencyType::IntraDIMMRank, "tRFC_dpr"}, @@ -600,13 +601,13 @@ DependencyMap TimeDependenciesInfoDDR5::mSpecializedGetDependencies() const { forward_as_tuple("PRESB"), forward_as_tuple( initializer_list{ - {tRAS + cmdLengthDiff, "ACT", DependencyType::IntraBankGroup, "tRAS + tCK"}, - {tRTP + cmdLengthDiff, "RD", DependencyType::IntraBankGroup, "tRTP + tCK"}, - {tRTP + cmdLengthDiff, "RDA", DependencyType::IntraBankGroup, "tRTP + tCK"}, - {tWRPRE + cmdLengthDiff, "WR", DependencyType::IntraBankGroup, "tWRPRE + tCK"}, - {tWRPRE + cmdLengthDiff + tBURST16, "WR", DependencyType::IntraBankGroup, "tWRPRE + tCK + tBURST16"}, - {tWRPRE + cmdLengthDiff, "WRA", DependencyType::IntraBankGroup, "tWRPRE + tCK"}, - {tWRPRE + cmdLengthDiff + tBURST16, "WRA", DependencyType::IntraBankGroup, "tWRPRE + tCK + tBURST16"}, + {tRAS + cmdLengthDiff, "ACT", DependencyType::IntraBankInGroup, "tRAS + tCK"}, + {tRTP + cmdLengthDiff, "RD", DependencyType::IntraBankInGroup, "tRTP + tCK"}, + {tRTP + cmdLengthDiff, "RDA", DependencyType::IntraBankInGroup, "tRTP + tCK"}, + {tWRPRE + cmdLengthDiff, "WR", DependencyType::IntraBankInGroup, "tWRPRE + tCK"}, + {tWRPRE + cmdLengthDiff + tBURST16, "WR", DependencyType::IntraBankInGroup, "tWRPRE + tCK + tBURST16"}, + {tWRPRE + cmdLengthDiff, "WRA", DependencyType::IntraBankInGroup, "tWRPRE + tCK"}, + {tWRPRE + cmdLengthDiff + tBURST16, "WRA", DependencyType::IntraBankInGroup, "tWRPRE + tCK + tBURST16"}, {tPPD, "PREPB", DependencyType::IntraPhysicalRank, "tPPD"}, {tPPD, "PREAB", DependencyType::IntraPhysicalRank, "tPPD"}, {tCK, "CMD_BUS", DependencyType::InterDIMMRank, "CommandBus"}, diff --git a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR5.h b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR5.h index e07bb7ad..f17513ab 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR5.h +++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR5.h @@ -44,6 +44,7 @@ class TimeDependenciesInfoDDR5 final : public DRAMTimeDependenciesBase { static const std::vector getPossiblePhases(); void rankIDToRankIDs(size_t rankID, size_t& dimmRID, size_t& physRID, size_t& logRID) const; + void bankIDToBankInGroup(size_t logicalRankID, size_t bankID, size_t& bankInGroup) const; protected: void mInitializeValues() override; @@ -52,8 +53,9 @@ class TimeDependenciesInfoDDR5 final : public DRAMTimeDependenciesBase { protected: uint mNumOfRanks; uint mNumOfDIMMRanks; - uint mNumOfPhysicalRanks; - uint mNumOfLogicalRanks; + uint mNumLogicalRanksPerPhysicalRank; + uint mNumPhysicalRanksPerDIMMRank; + uint mNumBanksPerGroup; uint burstLength; uint dataRate; @@ -139,13 +141,5 @@ class TimeDependenciesInfoDDR5 final : public DRAMTimeDependenciesBase { uint tBURST16; uint tBURST32; - - protected: - uint mBitsDIMMRanks; - uint mBitsPhysicalRanks; - uint mBitsLogicalRanks; - uint mLogRankMask; - uint mPhysRankMask; - uint mDIMMRankMask; }; diff --git a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/phasedependenciestracker.cpp b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/phasedependenciestracker.cpp index e2ba2d9b..a9d0f80b 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/phasedependenciestracker.cpp +++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/phasedependenciestracker.cpp @@ -261,9 +261,17 @@ PhaseDependenciesTracker::mCalculateDependencies(const std::shared_ptrid, otherPhase->phaseName.getIDStr() }); - } + } else if (timeDiff < dep.timeValue && dep.phaseDep == StringMapper::Identifier::CMD_BUS) { + poolController.push(dep.phaseDep, DBDependencyEntry{ + phase->id, + phase->phaseName.getIDStr(), + PhaseDependency::dependencyTypeName(dep.depType), + dep.timeDepName, + otherPhase->id, + otherPhase->phaseName.getIDStr() + }); - if (timeDiff < dep.timeValue) { + } else if (timeDiff < dep.timeValue) { poolController.increment(dep.phaseDep); } diff --git a/DRAMSys/traceAnalyzer/businessObjects/phases/phasedependency.cpp b/DRAMSys/traceAnalyzer/businessObjects/phases/phasedependency.cpp index 0cd7ec0e..5b30c638 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/phases/phasedependency.cpp +++ b/DRAMSys/traceAnalyzer/businessObjects/phases/phasedependency.cpp @@ -138,6 +138,9 @@ QString PhaseDependency::dependencyTypeName(DependencyType dtype) { case IntraBankGroup: return "IntraBankGroup"; + + case IntraBankInGroup: + return "IntraBankInGroup"; case IntraRank: return "IntraRank"; diff --git a/DRAMSys/traceAnalyzer/businessObjects/phases/phasedependency.h b/DRAMSys/traceAnalyzer/businessObjects/phases/phasedependency.h index a29a67dd..86c4308a 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/phases/phasedependency.h +++ b/DRAMSys/traceAnalyzer/businessObjects/phases/phasedependency.h @@ -50,6 +50,7 @@ enum DependencyType { IntraBank, IntraBankGroup, + IntraBankInGroup, IntraRank, IntraLogicalRank, IntraPhysicalRank,