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numbers and bools written without string quotes

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This commit is contained in:
scorrea
2020-05-20 11:13:48 +02:00
parent b6f9c27722
commit efdfd7fc3d
44 changed files with 589 additions and 576 deletions
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10
DRAMSys/library/resources/configs/mcconfigs/fifo.json
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@@ -1,11 +1,11 @@
{"mcconfig": {"PagePolicy": "Open", {"mcconfig": {"PagePolicy": "Open",
"Scheduler": "Fifo", "Scheduler": "Fifo",
"RequestBufferSize": "8", "RequestBufferSize": 8,
"CmdMux": "Oldest", "CmdMux": "Oldest",
"RespQueue": "Fifo", "RespQueue": "Fifo",
"RefreshPolicy": "Rankwise", "RefreshPolicy": "Rankwise",
"RefreshMode": "1", "RefreshMode": 1,
"RefreshMaxPostponed": "8", "RefreshMaxPostponed": 8,
"RefreshMaxPulledin": "8", "RefreshMaxPulledin": 8,
"PowerDownPolicy": "NoPowerDown", "PowerDownPolicy": "NoPowerDown",
"PowerDownTimeout": "100"}} "PowerDownTimeout": 100}}

10
DRAMSys/library/resources/configs/mcconfigs/fifoStrict.json
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@@ -1,11 +1,11 @@
{"mcconfig": {"PagePolicy": "Open", {"mcconfig": {"PagePolicy": "Open",
"Scheduler": "Fifo", "Scheduler": "Fifo",
"RequestBufferSize": "8", "RequestBufferSize": 8,
"CmdMux": "Strict", "CmdMux": "Strict",
"RespQueue": "Fifo", "RespQueue": "Fifo",
"RefreshPolicy": "Rankwise", "RefreshPolicy": "Rankwise",
"RefreshMode": "1", "RefreshMode": 1,
"RefreshMaxPostponed": "8", "RefreshMaxPostponed": 8,
"RefreshMaxPulledin": "8", "RefreshMaxPulledin": 8,
"PowerDownPolicy": "NoPowerDown", "PowerDownPolicy": "NoPowerDown",
"PowerDownTimeout": "100"}} "PowerDownTimeout": 100}}

12
DRAMSys/library/resources/configs/mcconfigs/fr_fcfs.json
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@@ -1,2 +1,12 @@
{"mcconfig": { {"mcconfig": {
"PagePolicy": "Open", "Scheduler": "FrFcfs", "RequestBufferSize": "8", "CmdMux": "Oldest", "RespQueue": "Fifo", "RefreshPolicy": "Rankwise", "RefreshMode": "1", "RefreshMaxPostponed": "8", "RefreshMaxPulledin": "8", "PowerDownPolicy": "NoPowerDown", "PowerDownTimeout": "100"}} "PagePolicy": "Open",
"Scheduler": "FrFcfs",
"RequestBufferSize": 8,
"CmdMux": "Oldest",
"RespQueue": "Fifo",
"RefreshPolicy": "Rankwise",
"RefreshMode": 1,
"RefreshMaxPostponed": 8,
"RefreshMaxPulledin": 8,
"PowerDownPolicy": "NoPowerDown",
"PowerDownTimeout": 100}}

13
DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_grp.json
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@@ -1 +1,12 @@
{"mcconfig": {"PagePolicy": "Open", "Scheduler": "FrFcfsGrp", "RequestBufferSize": "8", "CmdMux": "Oldest", "RespQueue": "Fifo", "RefreshPolicy": "Rankwise", "RefreshMode": "1", "RefreshMaxPostponed": "8", "RefreshMaxPulledin": "8", "PowerDownPolicy": "NoPowerDown", "PowerDownTimeout": "100"}} {"mcconfig":
{"PagePolicy": "Open",
"Scheduler": "FrFcfsGrp",
"RequestBufferSize": 8,
"CmdMux": "Oldest",
"RespQueue": "Fifo",
"RefreshPolicy": "Rankwise",
"RefreshMode": 1,
"RefreshMaxPostponed": 8,
"RefreshMaxPulledin": 8,
"PowerDownPolicy": "NoPowerDown",
"PowerDownTimeout": 100}}

26
DRAMSys/library/resources/configs/simulator/ddr3-single-device.json
View File

@@ -1,21 +1,21 @@
{ {
"simconfig": { "simconfig": {
"AddressOffset": "0", "AddressOffset": 0,
"CheckTLM2Protocol": "0", "CheckTLM2Protocol": false,
"DatabaseRecording": "1", "DatabaseRecording": true,
"Debug": "0", "Debug": false,
"ECCControllerMode": "Disabled", "ECCControllerMode": "Disabled",
"EnableWindowing": "1", "EnableWindowing": true,
"ErrorCSVFile": "", "ErrorCSVFile": "",
"ErrorChipSeed": "42", "ErrorChipSeed": 42,
"NumberOfDevicesOnDIMM": "1", "NumberOfDevicesOnDIMM": 1,
"NumberOfMemChannels": "1", "NumberOfMemChannels": 1,
"PowerAnalysis": "1", "PowerAnalysis": true,
"SimulationName": "ddr3_single_dev", "SimulationName": "ddr3_single_dev",
"SimulationProgressBar": "1", "SimulationProgressBar": true,
"StoreMode": "NoStorage", "StoreMode": "NoStorage",
"ThermalSimulation": "0", "ThermalSimulation": false,
"UseMalloc": "0", "UseMalloc": false,
"WindowSize": "1000" "WindowSize": 1000
} }
} }

26
DRAMSys/library/resources/configs/simulator/ddr3.json
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@@ -1,21 +1,21 @@
{ {
"simconfig": { "simconfig": {
"AddressOffset": "0", "AddressOffset": 0,
"CheckTLM2Protocol": "0", "CheckTLM2Protocol": false,
"DatabaseRecording": "1", "DatabaseRecording": true,
"Debug": "0", "Debug": false,
"ECCControllerMode": "Disabled", "ECCControllerMode": "Disabled",
"EnableWindowing": "0", "EnableWindowing": false,
"ErrorCSVFile": "", "ErrorCSVFile": "",
"ErrorChipSeed": "42", "ErrorChipSeed": 42,
"NumberOfDevicesOnDIMM": "8", "NumberOfDevicesOnDIMM": 8,
"NumberOfMemChannels": "1", "NumberOfMemChannels": 1,
"PowerAnalysis": "0", "PowerAnalysis": false,
"SimulationName": "ddr3", "SimulationName": "ddr3",
"SimulationProgressBar": "1", "SimulationProgressBar": true,
"StoreMode": "NoStorage", "StoreMode": "NoStorage",
"ThermalSimulation": "0", "ThermalSimulation": false,
"UseMalloc": "0", "UseMalloc": false,
"WindowSize": "1000" "WindowSize": 1000
} }
} }

26
DRAMSys/library/resources/configs/simulator/ddr3_boot_linux.json
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@@ -1,21 +1,21 @@
{ {
"simconfig": { "simconfig": {
"AddressOffset": "2147483648", "AddressOffset": 2147483648,
"CheckTLM2Protocol": "0", "CheckTLM2Protocol": false,
"DatabaseRecording": "1", "DatabaseRecording": true,
"Debug": "0", "Debug": false,
"ECCControllerMode": "Disabled", "ECCControllerMode": "Disabled",
"EnableWindowing": "1", "EnableWindowing": true,
"ErrorCSVFile": "", "ErrorCSVFile": "",
"ErrorChipSeed": "42", "ErrorChipSeed": 42,
"NumberOfDevicesOnDIMM": "8", "NumberOfDevicesOnDIMM": 8,
"NumberOfMemChannels": "1", "NumberOfMemChannels": 1,
"PowerAnalysis": "1", "PowerAnalysis": true,
"SimulationName": "ddr3", "SimulationName": "ddr3",
"SimulationProgressBar": "1", "SimulationProgressBar": true,
"StoreMode": "Store", "StoreMode": "Store",
"ThermalSimulation": "0", "ThermalSimulation": false,
"UseMalloc": "1", "UseMalloc": true,
"WindowSize": "1000" "WindowSize": 1000
} }
} }

26
DRAMSys/library/resources/configs/simulator/ddr3_ecc.json
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@@ -1,21 +1,21 @@
{ {
"simconfig": { "simconfig": {
"AddressOffset": "0", "AddressOffset": 0,
"CheckTLM2Protocol": "0", "CheckTLM2Protocol": false,
"DatabaseRecording": "1", "DatabaseRecording": true,
"Debug": "0", "Debug": false,
"ECCControllerMode": "Hamming", "ECCControllerMode": "Hamming",
"EnableWindowing": "1", "EnableWindowing": true,
"ErrorCSVFile": "", "ErrorCSVFile": "",
"ErrorChipSeed": "42", "ErrorChipSeed": 42,
"NumberOfDevicesOnDIMM": "8", "NumberOfDevicesOnDIMM": 8,
"NumberOfMemChannels": "1", "NumberOfMemChannels": 1,
"PowerAnalysis": "1", "PowerAnalysis": true,
"SimulationName": "ddr3", "SimulationName": "ddr3",
"SimulationProgressBar": "1", "SimulationProgressBar": true,
"StoreMode": "ErrorModel", "StoreMode": "ErrorModel",
"ThermalSimulation": "0", "ThermalSimulation": false,
"UseMalloc": "0", "UseMalloc": false,
"WindowSize": "1000" "WindowSize": 1000
} }
} }

26
DRAMSys/library/resources/configs/simulator/ddr3_gem5_se.json
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@@ -1,21 +1,21 @@
{ {
"simconfig": { "simconfig": {
"AddressOffset": "0", "AddressOffset": 0,
"CheckTLM2Protocol": "0", "CheckTLM2Protocol": false,
"DatabaseRecording": "1", "DatabaseRecording": true,
"Debug": "0", "Debug": false,
"ECCControllerMode": "Disabled", "ECCControllerMode": "Disabled",
"EnableWindowing": "1", "EnableWindowing": true,
"ErrorCSVFile": "", "ErrorCSVFile": "",
"ErrorChipSeed": "42", "ErrorChipSeed": 42,
"NumberOfDevicesOnDIMM": "8", "NumberOfDevicesOnDIMM": 8,
"NumberOfMemChannels": "1", "NumberOfMemChannels": 1,
"PowerAnalysis": "1", "PowerAnalysis": true,
"SimulationName": "ddr3", "SimulationName": "ddr3",
"SimulationProgressBar": "1", "SimulationProgressBar": true,
"StoreMode": "Store", "StoreMode": "Store",
"ThermalSimulation": "0", "ThermalSimulation": false,
"UseMalloc": "0", "UseMalloc": false,
"WindowSize": "1000" "WindowSize": 1000
} }
} }

26
DRAMSys/library/resources/configs/simulator/ddr4.json
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@@ -1,21 +1,21 @@
{ {
"simconfig": { "simconfig": {
"AddressOffset": "0", "AddressOffset": 0,
"CheckTLM2Protocol": "0", "CheckTLM2Protocol": false,
"DatabaseRecording": "1", "DatabaseRecording": true,
"Debug": "0", "Debug": false,
"ECCControllerMode": "Disabled", "ECCControllerMode": "Disabled",
"EnableWindowing": "0", "EnableWindowing": false,
"ErrorCSVFile": "", "ErrorCSVFile": "",
"ErrorChipSeed": "42", "ErrorChipSeed": 42,
"NumberOfDevicesOnDIMM": "8", "NumberOfDevicesOnDIMM": 8,
"NumberOfMemChannels": "1", "NumberOfMemChannels": 1,
"PowerAnalysis": "0", "PowerAnalysis": false,
"SimulationName": "ddr4", "SimulationName": "ddr4",
"SimulationProgressBar": "1", "SimulationProgressBar": true,
"StoreMode": "NoStorage", "StoreMode": "NoStorage",
"ThermalSimulation": "0", "ThermalSimulation": false,
"UseMalloc": "0", "UseMalloc": false,
"WindowSize": "1000" "WindowSize": 1000
} }
} }

26
DRAMSys/library/resources/configs/simulator/hbm2.json
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@@ -1,21 +1,21 @@
{ {
"simconfig": { "simconfig": {
"AddressOffset": "0", "AddressOffset": 0,
"CheckTLM2Protocol": "0", "CheckTLM2Protocol": false,
"DatabaseRecording": "1", "DatabaseRecording": true,
"Debug": "0", "Debug": false,
"ECCControllerMode": "Disabled", "ECCControllerMode": "Disabled",
"EnableWindowing": "0", "EnableWindowing": false,
"ErrorCSVFile": "", "ErrorCSVFile": "",
"ErrorChipSeed": "42", "ErrorChipSeed": 42,
"NumberOfDevicesOnDIMM": "1", "NumberOfDevicesOnDIMM": 1,
"NumberOfMemChannels": "1", "NumberOfMemChannels": 1,
"PowerAnalysis": "0", "PowerAnalysis": false,
"SimulationName": "hbm2", "SimulationName": "hbm2",
"SimulationProgressBar": "1", "SimulationProgressBar": true,
"StoreMode": "NoStorage", "StoreMode": "NoStorage",
"ThermalSimulation": "0", "ThermalSimulation": false,
"UseMalloc": "0", "UseMalloc": false,
"WindowSize": "1000" "WindowSize": 1000
} }
} }

26
DRAMSys/library/resources/configs/simulator/lpddr4.json
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@@ -1,21 +1,21 @@
{ {
"simconfig": { "simconfig": {
"AddressOffset": "0", "AddressOffset": 0,
"CheckTLM2Protocol": "0", "CheckTLM2Protocol": false,
"DatabaseRecording": "1", "DatabaseRecording": true,
"Debug": "0", "Debug": false,
"ECCControllerMode": "Disabled", "ECCControllerMode": "Disabled",
"EnableWindowing": "0", "EnableWindowing": false,
"ErrorCSVFile": "", "ErrorCSVFile": "",
"ErrorChipSeed": "42", "ErrorChipSeed": 42,
"NumberOfDevicesOnDIMM": "1", "NumberOfDevicesOnDIMM": 1,
"NumberOfMemChannels": "1", "NumberOfMemChannels": 1,
"PowerAnalysis": "0", "PowerAnalysis": false,
"SimulationName": "lpddr4", "SimulationName": "lpddr4",
"SimulationProgressBar": "1", "SimulationProgressBar": true,
"StoreMode": "NoStorage", "StoreMode": "NoStorage",
"ThermalSimulation": "0", "ThermalSimulation": false,
"UseMalloc": "0", "UseMalloc": false,
"WindowSize": "1000" "WindowSize": 1000
} }
} }

70
DRAMSys/library/resources/configs/simulator/orgr.json
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@@ -1,40 +1,40 @@
{ {
"simconfig": { "simconfig": {
"ControllerCoreRGR": "1", "ControllerCoreRGR": true,
"ControllerCoreRGRB0": "1", "ControllerCoreRGRB0": true,
"ControllerCoreRGRB1": "1", "ControllerCoreRGRB1": true,
"ControllerCoreRGRB10": "0", "ControllerCoreRGRB10": false,
"ControllerCoreRGRB11": "0", "ControllerCoreRGRB11": false,
"ControllerCoreRGRB12": "0", "ControllerCoreRGRB12": false,
"ControllerCoreRGRB13": "0", "ControllerCoreRGRB13": false,
"ControllerCoreRGRB14": "0", "ControllerCoreRGRB14": false,
"ControllerCoreRGRB15": "0", "ControllerCoreRGRB15": false,
"ControllerCoreRGRB2": "1", "ControllerCoreRGRB2": true,
"ControllerCoreRGRB3": "1", "ControllerCoreRGRB3": true,
"ControllerCoreRGRB4": "1", "ControllerCoreRGRB4": true,
"ControllerCoreRGRB5": "1", "ControllerCoreRGRB5": true,
"ControllerCoreRGRB6": "1", "ControllerCoreRGRB6": true,
"ControllerCoreRGRB7": "1", "ControllerCoreRGRB7": true,
"ControllerCoreRGRB8": "0", "ControllerCoreRGRB8": false,
"ControllerCoreRGRB9": "0", "ControllerCoreRGRB9": false,
"ControllerCoreRGRtFAWBInClkCycles": "27", "ControllerCoreRGRtFAWBInClkCycles": 27,
"ControllerCoreRGRtRASBInClkCycles": "20", "ControllerCoreRGRtRASBInClkCycles": 20,
"ControllerCoreRGRtRCBInClkCycles": "27", "ControllerCoreRGRtRCBInClkCycles": 27,
"ControllerCoreRGRtRPBInClkCycles": "8", "ControllerCoreRGRtRPBInClkCycles": 8,
"ControllerCoreRGRtRRDB_LInClkCycles": "6", "ControllerCoreRGRtRRDB_LInClkCycles": 6,
"ControllerCoreRGRtRRDB_SInClkCycles": "6", "ControllerCoreRGRtRRDB_SInClkCycles": 6,
"ControllerCoreRefDisable": "0", "ControllerCoreRefDisable": 0,
"ControllerCoreRefNumARCmdsIntREFI": "8192", "ControllerCoreRefNumARCmdsIntREFI": 8192,
"DatabaseRecording": "1", "DatabaseRecording": true,
"Debug": "0", "Debug": false,
"EnableWindowing": "1", "EnableWindowing": true,
"NumberOfDevicesOnDIMM": "4", "NumberOfDevicesOnDIMM": 4,
"NumberOfMemChannels": "1", "NumberOfMemChannels": 1,
"PowerAnalysis": "1", "PowerAnalysis": true,
"SimulationName": "orgr", "SimulationName": "orgr",
"SimulationProgressBar": "1", "SimulationProgressBar": true,
"ThermalSimulation": "0", "ThermalSimulation": false,
"UseMalloc": "0", "UseMalloc": false,
"WindowSize": "1000" "WindowSize": 1000
} }
} }

72
DRAMSys/library/resources/configs/simulator/orgr_4b_opt_timings_ddr3.json
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@@ -1,40 +1,40 @@
{ {
"simconfig": { "simconfig": {
"ControllerCoreRGR": "1", "ControllerCoreRGR": true,
"ControllerCoreRGRB0": "1", "ControllerCoreRGRB0": true,
"ControllerCoreRGRB1": "1", "ControllerCoreRGRB1": true,
"ControllerCoreRGRB10": "0", "ControllerCoreRGRB10": false,
"ControllerCoreRGRB11": "0", "ControllerCoreRGRB11": false,
"ControllerCoreRGRB12": "0", "ControllerCoreRGRB12": false,
"ControllerCoreRGRB13": "0", "ControllerCoreRGRB13": false,
"ControllerCoreRGRB14": "0", "ControllerCoreRGRB14": false,
"ControllerCoreRGRB15": "0", "ControllerCoreRGRB15": false,
"ControllerCoreRGRB2": "1", "ControllerCoreRGRB2": true,
"ControllerCoreRGRB3": "1", "ControllerCoreRGRB3": true,
"ControllerCoreRGRB4": "0", "ControllerCoreRGRB4": false,
"ControllerCoreRGRB5": "0", "ControllerCoreRGRB5": false,
"ControllerCoreRGRB6": "0", "ControllerCoreRGRB6": false,
"ControllerCoreRGRB7": "0", "ControllerCoreRGRB7": false,
"ControllerCoreRGRB8": "0", "ControllerCoreRGRB8": false,
"ControllerCoreRGRB9": "0", "ControllerCoreRGRB9": false,
"ControllerCoreRGRtFAWBInClkCycles": "0", "ControllerCoreRGRtFAWBInClkCycles": 0,
"ControllerCoreRGRtRASBInClkCycles": "11", "ControllerCoreRGRtRASBInClkCycles": 11,
"ControllerCoreRGRtRCBInClkCycles": "16", "ControllerCoreRGRtRCBInClkCycles": 16,
"ControllerCoreRGRtRPBInClkCycles": "5", "ControllerCoreRGRtRPBInClkCycles": 5,
"ControllerCoreRGRtRRDB_LInClkCycles": "2", "ControllerCoreRGRtRRDB_LInClkCycles": 2,
"ControllerCoreRGRtRRDB_SInClkCycles": "2", "ControllerCoreRGRtRRDB_SInClkCycles": 2,
"ControllerCoreRefDisable": "0", "ControllerCoreRefDisable": 0,
"ControllerCoreRefNumARCmdsIntREFI": "8192", "ControllerCoreRefNumARCmdsIntREFI": 8192,
"DatabaseRecording": "1", "DatabaseRecording": true,
"Debug": "0", "Debug": false,
"EnableWindowing": "1", "EnableWindowing": true,
"NumberOfDevicesOnDIMM": "4", "NumberOfDevicesOnDIMM": 4,
"NumberOfMemChannels": "1", "NumberOfMemChannels": 1,
"PowerAnalysis": "1", "PowerAnalysis": true,
"SimulationName": "orgr_4b_opt_timings", "SimulationName": "orgr_4b_opt_timings",
"SimulationProgressBar": "1", "SimulationProgressBar": true,
"ThermalSimulation": "0", "ThermalSimulation": false,
"UseMalloc": "0", "UseMalloc": false,
"WindowSize": "1000" "WindowSize": 1000
} }
} }

74
DRAMSys/library/resources/configs/simulator/orgr_4b_std_timings_ddr3.json
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@@ -1,42 +1,40 @@
{ {
"simconfig": { "simconfig": {
"ControllerCoreRGR": { "ControllerCoreRGR": true,
"@value": "1" "ControllerCoreRGRB0": true,
}, "ControllerCoreRGRB1": true,
"ControllerCoreRGRB0": "1", "ControllerCoreRGRB10": false,
"ControllerCoreRGRB1": "1", "ControllerCoreRGRB11": false,
"ControllerCoreRGRB10": "0", "ControllerCoreRGRB12": false,
"ControllerCoreRGRB11": "0", "ControllerCoreRGRB13": false,
"ControllerCoreRGRB12": "0", "ControllerCoreRGRB14": false,
"ControllerCoreRGRB13": "0", "ControllerCoreRGRB15": false,
"ControllerCoreRGRB14": "0", "ControllerCoreRGRB2": true,
"ControllerCoreRGRB15": "0", "ControllerCoreRGRB3": true,
"ControllerCoreRGRB2": "1", "ControllerCoreRGRB4": false,
"ControllerCoreRGRB3": "1", "ControllerCoreRGRB5": false,
"ControllerCoreRGRB4": "0", "ControllerCoreRGRB6": false,
"ControllerCoreRGRB5": "0", "ControllerCoreRGRB7": false,
"ControllerCoreRGRB6": "0", "ControllerCoreRGRB8": false,
"ControllerCoreRGRB7": "0", "ControllerCoreRGRB9": false,
"ControllerCoreRGRB8": "0", "ControllerCoreRGRtFAWBInClkCycles": 27,
"ControllerCoreRGRB9": "0", "ControllerCoreRGRtRASBInClkCycles": 20,
"ControllerCoreRGRtFAWBInClkCycles": "27", "ControllerCoreRGRtRCBInClkCycles": 27,
"ControllerCoreRGRtRASBInClkCycles": "20", "ControllerCoreRGRtRPBInClkCycles": 8,
"ControllerCoreRGRtRCBInClkCycles": "27", "ControllerCoreRGRtRRDB_LInClkCycles": 6,
"ControllerCoreRGRtRPBInClkCycles": "8", "ControllerCoreRGRtRRDB_SInClkCycles": 6,
"ControllerCoreRGRtRRDB_LInClkCycles": "6", "ControllerCoreRefDisable": 0,
"ControllerCoreRGRtRRDB_SInClkCycles": "6", "ControllerCoreRefNumARCmdsIntREFI": 8192,
"ControllerCoreRefDisable": "0", "DatabaseRecording": true,
"ControllerCoreRefNumARCmdsIntREFI": "8192", "Debug": false,
"DatabaseRecording": "1", "EnableWindowing": true,
"Debug": "0", "NumberOfDevicesOnDIMM": 4,
"EnableWindowing": "1", "NumberOfMemChannels": 1,
"NumberOfDevicesOnDIMM": "4", "PowerAnalysis": true,
"NumberOfMemChannels": "1",
"PowerAnalysis": "1",
"SimulationName": "orgr_4b_std_timings", "SimulationName": "orgr_4b_std_timings",
"SimulationProgressBar": "1", "SimulationProgressBar": true,
"ThermalSimulation": "0", "ThermalSimulation": false,
"UseMalloc": "0", "UseMalloc": false,
"WindowSize": "1000" "WindowSize": 1000
} }
} }

72
DRAMSys/library/resources/configs/simulator/orgr_8b_opt_timings_ddr3.json
View File

@@ -1,40 +1,40 @@
{ {
"simconfig": { "simconfig": {
"ControllerCoreRGR": "1", "ControllerCoreRGR": true,
"ControllerCoreRGRB0": "1", "ControllerCoreRGRB0": true,
"ControllerCoreRGRB1": "1", "ControllerCoreRGRB1": true,
"ControllerCoreRGRB10": "0", "ControllerCoreRGRB10": false,
"ControllerCoreRGRB11": "0", "ControllerCoreRGRB11": false,
"ControllerCoreRGRB12": "0", "ControllerCoreRGRB12": false,
"ControllerCoreRGRB13": "0", "ControllerCoreRGRB13": false,
"ControllerCoreRGRB14": "0", "ControllerCoreRGRB14": false,
"ControllerCoreRGRB15": "0", "ControllerCoreRGRB15": false,
"ControllerCoreRGRB2": "1", "ControllerCoreRGRB2": true,
"ControllerCoreRGRB3": "1", "ControllerCoreRGRB3": true,
"ControllerCoreRGRB4": "1", "ControllerCoreRGRB4": true,
"ControllerCoreRGRB5": "1", "ControllerCoreRGRB5": true,
"ControllerCoreRGRB6": "1", "ControllerCoreRGRB6": true,
"ControllerCoreRGRB7": "1", "ControllerCoreRGRB7": true,
"ControllerCoreRGRB8": "0", "ControllerCoreRGRB8": false,
"ControllerCoreRGRB9": "0", "ControllerCoreRGRB9": false,
"ControllerCoreRGRtFAWBInClkCycles": "0", "ControllerCoreRGRtFAWBInClkCycles": 0,
"ControllerCoreRGRtRASBInClkCycles": "11", "ControllerCoreRGRtRASBInClkCycles": 11,
"ControllerCoreRGRtRCBInClkCycles": "16", "ControllerCoreRGRtRCBInClkCycles": 16,
"ControllerCoreRGRtRPBInClkCycles": "5", "ControllerCoreRGRtRPBInClkCycles": 5,
"ControllerCoreRGRtRRDB_LInClkCycles": "2", "ControllerCoreRGRtRRDB_LInClkCycles": 2,
"ControllerCoreRGRtRRDB_SInClkCycles": "2", "ControllerCoreRGRtRRDB_SInClkCycles": 2,
"ControllerCoreRefDisable": "0", "ControllerCoreRefDisable": 0,
"ControllerCoreRefNumARCmdsIntREFI": "8192", "ControllerCoreRefNumARCmdsIntREFI": 8192,
"DatabaseRecording": "1", "DatabaseRecording": true,
"Debug": "0", "Debug": false,
"EnableWindowing": "1", "EnableWindowing": true,
"NumberOfDevicesOnDIMM": "4", "NumberOfDevicesOnDIMM": 4,
"NumberOfMemChannels": "1", "NumberOfMemChannels": 1,
"PowerAnalysis": "1", "PowerAnalysis": true,
"SimulationName": "orgr_8b_opt_timings", "SimulationName": "orgr_8b_opt_timings",
"SimulationProgressBar": "1", "SimulationProgressBar": true,
"ThermalSimulation": "0", "ThermalSimulation": false,
"UseMalloc": "0", "UseMalloc": false,
"WindowSize": "1000" "WindowSize": 1000
} }
} }

74
DRAMSys/library/resources/configs/simulator/orgr_8b_std_timings_ddr3.json
View File

@@ -1,42 +1,40 @@
{ {
"simconfig": { "simconfig": {
"ControllerCoreRGR": { "ControllerCoreRGR": true,
"@value": "1" "ControllerCoreRGRB0": true,
}, "ControllerCoreRGRB1": true,
"ControllerCoreRGRB0": "1", "ControllerCoreRGRB10": false,
"ControllerCoreRGRB1": "1", "ControllerCoreRGRB11": false,
"ControllerCoreRGRB10": "0", "ControllerCoreRGRB12": false,
"ControllerCoreRGRB11": "0", "ControllerCoreRGRB13": false,
"ControllerCoreRGRB12": "0", "ControllerCoreRGRB14": false,
"ControllerCoreRGRB13": "0", "ControllerCoreRGRB15": false,
"ControllerCoreRGRB14": "0", "ControllerCoreRGRB2": true,
"ControllerCoreRGRB15": "0", "ControllerCoreRGRB3": true,
"ControllerCoreRGRB2": "1", "ControllerCoreRGRB4": true,
"ControllerCoreRGRB3": "1", "ControllerCoreRGRB5": true,
"ControllerCoreRGRB4": "1", "ControllerCoreRGRB6": true,
"ControllerCoreRGRB5": "1", "ControllerCoreRGRB7": true,
"ControllerCoreRGRB6": "1", "ControllerCoreRGRB8": false,
"ControllerCoreRGRB7": "1", "ControllerCoreRGRB9": false,
"ControllerCoreRGRB8": "0", "ControllerCoreRGRtFAWBInClkCycles": 27,
"ControllerCoreRGRB9": "0", "ControllerCoreRGRtRASBInClkCycles": 20,
"ControllerCoreRGRtFAWBInClkCycles": "27", "ControllerCoreRGRtRCBInClkCycles": 27,
"ControllerCoreRGRtRASBInClkCycles": "20", "ControllerCoreRGRtRPBInClkCycles": 8,
"ControllerCoreRGRtRCBInClkCycles": "27", "ControllerCoreRGRtRRDB_LInClkCycles": 6,
"ControllerCoreRGRtRPBInClkCycles": "8", "ControllerCoreRGRtRRDB_SInClkCycles": 6,
"ControllerCoreRGRtRRDB_LInClkCycles": "6", "ControllerCoreRefDisable": 0,
"ControllerCoreRGRtRRDB_SInClkCycles": "6", "ControllerCoreRefNumARCmdsIntREFI": 8192,
"ControllerCoreRefDisable": "0", "DatabaseRecording": true,
"ControllerCoreRefNumARCmdsIntREFI": "8192", "Debug": false,
"DatabaseRecording": "1", "EnableWindowing": true,
"Debug": "0", "NumberOfDevicesOnDIMM": 4,
"EnableWindowing": "1", "NumberOfMemChannels": 1,
"NumberOfDevicesOnDIMM": "4", "PowerAnalysis": true,
"NumberOfMemChannels": "1",
"PowerAnalysis": "1",
"SimulationName": "orgr_8b_std_timings_ddr3", "SimulationName": "orgr_8b_std_timings_ddr3",
"SimulationProgressBar": "1", "SimulationProgressBar": true,
"ThermalSimulation": "0", "ThermalSimulation": false,
"UseMalloc": "0", "UseMalloc": false,
"WindowSize": "1000" "WindowSize": 1000
} }
} }

26
DRAMSys/library/resources/configs/simulator/orgr_ddr4.json
View File

@@ -1,21 +1,21 @@
{ {
"simconfig": { "simconfig": {
"AddressOffset": "0", "AddressOffset": 0,
"CheckTLM2Protocol": "0", "CheckTLM2Protocol": false,
"DatabaseRecording": "1", "DatabaseRecording": true,
"Debug": "0", "Debug": false,
"ECCControllerMode": "Disabled", "ECCControllerMode": "Disabled",
"EnableWindowing": "1", "EnableWindowing": true,
"ErrorCSVFile": "", "ErrorCSVFile": "",
"ErrorChipSeed": "42", "ErrorChipSeed": 42,
"NumberOfDevicesOnDIMM": "4", "NumberOfDevicesOnDIMM": 4,
"NumberOfMemChannels": "1", "NumberOfMemChannels": 1,
"PowerAnalysis": "1", "PowerAnalysis": true,
"SimulationName": "orgr_ddr4", "SimulationName": "orgr_ddr4",
"SimulationProgressBar": "1", "SimulationProgressBar": true,
"StoreMode": "NoStorage", "StoreMode": "NoStorage",
"ThermalSimulation": "0", "ThermalSimulation": false,
"UseMalloc": "0", "UseMalloc": false,
"WindowSize": "1000" "WindowSize": 1000
} }
} }

26
DRAMSys/library/resources/configs/simulator/rgrsimcfg-gem5-fs.json
View File

@@ -1,21 +1,21 @@
{ {
"simconfig": { "simconfig": {
"AddressOffset": "2147483648", "AddressOffset": 2147483648,
"CheckTLM2Protocol": "0", "CheckTLM2Protocol": false,
"DatabaseRecording": "0", "DatabaseRecording": false,
"Debug": "0", "Debug": false,
"ECCControllerMode": "Disabled", "ECCControllerMode": "Disabled",
"EnableWindowing": "1", "EnableWindowing": true,
"ErrorCSVFile": "", "ErrorCSVFile": "",
"ErrorChipSeed": "42", "ErrorChipSeed": 42,
"NumberOfDevicesOnDIMM": "4", "NumberOfDevicesOnDIMM": 4,
"NumberOfMemChannels": "1", "NumberOfMemChannels": 1,
"PowerAnalysis": "1", "PowerAnalysis": true,
"SimulationName": "rgr", "SimulationName": "rgr",
"SimulationProgressBar": "1", "SimulationProgressBar": true,
"StoreMode": "Store", "StoreMode": "Store",
"ThermalSimulation": "0", "ThermalSimulation": false,
"UseMalloc": "1", "UseMalloc": true,
"WindowSize": "1000" "WindowSize": 1000
} }
} }

26
DRAMSys/library/resources/configs/simulator/rgrsimcfg-gem5-se.json
View File

@@ -1,21 +1,21 @@
{ {
"simconfig": { "simconfig": {
"AddressOffset": "0", "AddressOffset": 0,
"CheckTLM2Protocol": "0", "CheckTLM2Protocol": false,
"DatabaseRecording": "1", "DatabaseRecording": true,
"Debug": "0", "Debug": false,
"ECCControllerMode": "Disabled", "ECCControllerMode": "Disabled",
"EnableWindowing": "1", "EnableWindowing": true,
"ErrorCSVFile": "", "ErrorCSVFile": "",
"ErrorChipSeed": "42", "ErrorChipSeed": 42,
"NumberOfDevicesOnDIMM": "4", "NumberOfDevicesOnDIMM": 4,
"NumberOfMemChannels": "1", "NumberOfMemChannels": 1,
"PowerAnalysis": "1", "PowerAnalysis": true,
"SimulationName": "rgr", "SimulationName": "rgr",
"SimulationProgressBar": "1", "SimulationProgressBar": true,
"StoreMode": "Store", "StoreMode": "Store",
"ThermalSimulation": "0", "ThermalSimulation": false,
"UseMalloc": "0", "UseMalloc": false,
"WindowSize": "1000" "WindowSize": 1000
} }
} }

26
DRAMSys/library/resources/configs/simulator/rgrsimcfg.json
View File

@@ -1,21 +1,21 @@
{ {
"simconfig": { "simconfig": {
"AddressOffset": "0", "AddressOffset": 0,
"CheckTLM2Protocol": "0", "CheckTLM2Protocol": false,
"DatabaseRecording": "1", "DatabaseRecording": true,
"Debug": "0", "Debug": false,
"ECCControllerMode": "Disabled", "ECCControllerMode": "Disabled",
"EnableWindowing": "1", "EnableWindowing": true,
"ErrorCSVFile": "", "ErrorCSVFile": "",
"ErrorChipSeed": "42", "ErrorChipSeed": 42,
"NumberOfDevicesOnDIMM": "4", "NumberOfDevicesOnDIMM": 4,
"NumberOfMemChannels": "1", "NumberOfMemChannels": 1,
"PowerAnalysis": "1", "PowerAnalysis": true,
"SimulationName": "rgr", "SimulationName": "rgr",
"SimulationProgressBar": "1", "SimulationProgressBar": true,
"StoreMode": "NoStorage", "StoreMode": "NoStorage",
"ThermalSimulation": "0", "ThermalSimulation": false,
"UseMalloc": "0", "UseMalloc": false,
"WindowSize": "1000" "WindowSize": 1000
} }
} }

22
DRAMSys/library/resources/configs/simulator/sms.json
View File

@@ -1,16 +1,16 @@
{ {
"simconfig": { "simconfig": {
"CheckTLM2Protocol": "0", "CheckTLM2Protocol": false,
"DatabaseRecording": "1", "DatabaseRecording": true,
"Debug": "0", "Debug": false,
"EnableWindowing": "1", "EnableWindowing": true,
"NumberOfDevicesOnDIMM": "1", "NumberOfDevicesOnDIMM": 1,
"NumberOfMemChannels": "4", "NumberOfMemChannels": 4,
"PowerAnalysis": "1", "PowerAnalysis": true,
"SimulationName": "sms", "SimulationName": "sms",
"SimulationProgressBar": "1", "SimulationProgressBar": true,
"ThermalSimulation": "0", "ThermalSimulation": false,
"UseMalloc": "0", "UseMalloc": false,
"WindowSize": "1000" "WindowSize": 1000
} }
} }

24
DRAMSys/library/resources/configs/simulator/wideio.json
View File

@@ -1,20 +1,20 @@
{ {
"simconfig": { "simconfig": {
"CheckTLM2Protocol": "0", "CheckTLM2Protocol": false,
"DatabaseRecording": "1", "DatabaseRecording": true,
"Debug": "0", "Debug": false,
"ECCControllerMode": "Disabled", "ECCControllerMode": "Disabled",
"EnableWindowing": "1", "EnableWindowing": true,
"ErrorCSVFile": "../../DRAMSys/library/resources/error/wideio.csv", "ErrorCSVFile": "../../DRAMSys/library/resources/error/wideio.csv",
"ErrorChipSeed": "42", "ErrorChipSeed": 42,
"NumberOfDevicesOnDIMM": "1", "NumberOfDevicesOnDIMM": 1,
"NumberOfMemChannels": "4", "NumberOfMemChannels": 4,
"PowerAnalysis": "1", "PowerAnalysis": true,
"SimulationName": "wideio", "SimulationName": "wideio",
"SimulationProgressBar": "1", "SimulationProgressBar": true,
"StoreMode": "NoStorage", "StoreMode": "NoStorage",
"ThermalSimulation": "0", "ThermalSimulation": false,
"UseMalloc": "0", "UseMalloc": false,
"WindowSize": "1000" "WindowSize": 1000
} }
} }

24
DRAMSys/library/resources/configs/simulator/wideio_ecc.json
View File

@@ -1,20 +1,20 @@
{ {
"simconfig": { "simconfig": {
"CheckTLM2Protocol": "0", "CheckTLM2Protocol": false,
"DatabaseRecording": "1", "DatabaseRecording": true,
"Debug": "0", "Debug": false,
"ECCControllerMode": "Hamming", "ECCControllerMode": "Hamming",
"EnableWindowing": "1", "EnableWindowing": true,
"ErrorCSVFile": "../../DRAMSys/library/resources/error/wideio.csv", "ErrorCSVFile": "../../DRAMSys/library/resources/error/wideio.csv",
"ErrorChipSeed": "42", "ErrorChipSeed": 42,
"NumberOfDevicesOnDIMM": "1", "NumberOfDevicesOnDIMM": 1,
"NumberOfMemChannels": "1", "NumberOfMemChannels": 1,
"PowerAnalysis": "1", "PowerAnalysis": true,
"SimulationName": "wideio_ecc", "SimulationName": "wideio_ecc",
"SimulationProgressBar": "1", "SimulationProgressBar": true,
"StoreMode": "ErrorModel", "StoreMode": "ErrorModel",
"ThermalSimulation": "0", "ThermalSimulation": false,
"UseMalloc": "0", "UseMalloc": false,
"WindowSize": "1000" "WindowSize": 1000
} }
} }

24
DRAMSys/library/resources/configs/simulator/wideio_thermal.json
View File

@@ -1,20 +1,20 @@
{ {
"simconfig": { "simconfig": {
"CheckTLM2Protocol": "0", "CheckTLM2Protocol": false,
"DatabaseRecording": "1", "DatabaseRecording": true,
"Debug": "0", "Debug": false,
"ECCControllerMode": "Disabled", "ECCControllerMode": "Disabled",
"EnableWindowing": "1", "EnableWindowing": true,
"ErrorCSVFile": "../../DRAMSys/library/resources/error/wideio.csv", "ErrorCSVFile": "../../DRAMSys/library/resources/error/wideio.csv",
"ErrorChipSeed": "42", "ErrorChipSeed": 42,
"NumberOfDevicesOnDIMM": "1", "NumberOfDevicesOnDIMM": 1,
"NumberOfMemChannels": "1", "NumberOfMemChannels": 1,
"PowerAnalysis": "1", "PowerAnalysis": true,
"SimulationName": "wideio", "SimulationName": "wideio",
"SimulationProgressBar": "1", "SimulationProgressBar": true,
"StoreMode": "NoStorage", "StoreMode": "NoStorage",
"ThermalSimulation": "1", "ThermalSimulation": true,
"UseMalloc": "0", "UseMalloc": false,
"WindowSize": "1000" "WindowSize": 1000
} }
} }

14
DRAMSys/library/resources/configs/thermalsim/config.json
View File

@@ -1,15 +1,15 @@
{ {
"thermalsimconfig": { "thermalsimconfig": {
"TemperatureScale": "Celsius", "TemperatureScale": "Celsius",
"StaticTemperatureDefaultValue": "89", "StaticTemperatureDefaultValue": 89,
"ThermalSimPeriod":"100", "ThermalSimPeriod":100,
"ThermalSimUnit":"us", "ThermalSimUnit":"us",
"PowerInfoFile": "powerInfo.json", "PowerInfoFile": "powerInfo.json",
"IceServerIp": "127.0.0.1", "IceServerIp": "127.0.0.1",
"IceServerPort": "11880", "IceServerPort": 11880,
"SimPeriodAdjustFactor" : "10", "SimPeriodAdjustFactor" : 10,
"NPowStableCyclesToIncreasePeriod": "5", "NPowStableCyclesToIncreasePeriod": 5,
"GenerateTemperatureMap": "1", "GenerateTemperatureMap": true,
"GeneratePowerMap": "1" "GeneratePowerMap": true
} }
} }

16
DRAMSys/library/resources/configs/thermalsim/powerInfo.json
View File

@@ -1,20 +1,20 @@
{ {
"powerInfo": { "powerInfo": {
"dram_die_channel0": { "dram_die_channel0": {
"init_pow": "0", "init_pow": 0,
"threshold": "1.0" "threshold": 1.0
}, },
"dram_die_channel1": { "dram_die_channel1": {
"init_pow": "0", "init_pow": 0,
"threshold": "1.0" "threshold": 1.0
}, },
"dram_die_channel2": { "dram_die_channel2": {
"init_pow": "0", "init_pow": 0,
"threshold": "1.0" "threshold": 1.0
}, },
"dram_die_channel3": { "dram_die_channel3": {
"init_pow": "0", "init_pow": 0,
"threshold": "1.0" "threshold": 1.0
} }
} }
} }

4
DRAMSys/library/resources/simulations/ddr3-ecc.json
View File

@@ -8,9 +8,9 @@
"thermalconfig": "config.xml", "thermalconfig": "config.xml",
"tracesetup": [ "tracesetup": [
{ {
"clkMhz": "1000", "clkMhz": 1000,
"name": "test_ecc.stl" "name": "test_ecc.stl"
} }
] ]
} }
} }

4
DRAMSys/library/resources/simulations/ddr3-example.json
View File

@@ -8,9 +8,9 @@
"thermalconfig": "config.json", "thermalconfig": "config.json",
"tracesetup": [ "tracesetup": [
{ {
"clkMhz": "800", "clkMhz": 800,
"name": "ddr3_example.stl" "name": "ddr3_example.stl"
} }
] ]
} }
} }

6
DRAMSys/library/resources/simulations/ddr3-example2.json
View File

@@ -8,13 +8,13 @@
"thermalconfig": "config.xml", "thermalconfig": "config.xml",
"tracesetup": [ "tracesetup": [
{ {
"clkMhz": "300", "clkMhz": 300,
"name": "ddr3_example.stl" "name": "ddr3_example.stl"
}, },
{ {
"clkMhz": "400", "clkMhz": 400,
"name": "ddr3_example.stl" "name": "ddr3_example.stl"
} }
] ]
} }
} }

4
DRAMSys/library/resources/simulations/ddr3-single-device.json
View File

@@ -8,9 +8,9 @@
"thermalconfig": "config.xml", "thermalconfig": "config.xml",
"tracesetup": [ "tracesetup": [
{ {
"clkMhz": "200", "clkMhz": 200,
"name": "ddr3_single_dev_example.stl" "name": "ddr3_single_dev_example.stl"
} }
] ]
} }
} }

4
DRAMSys/library/resources/simulations/ddr3_postpone_ref_test.json
View File

@@ -8,9 +8,9 @@
"thermalconfig": "config.xml", "thermalconfig": "config.xml",
"tracesetup": [ "tracesetup": [
{ {
"clkMhz": "1000", "clkMhz": 1000,
"name": "ddr3_postpone_ref_test_1.stl" "name": "ddr3_postpone_ref_test_1.stl"
} }
] ]
} }
} }

4
DRAMSys/library/resources/simulations/ddr4-example.json
View File

@@ -8,9 +8,9 @@
"thermalconfig": "config.xml", "thermalconfig": "config.xml",
"tracesetup": [ "tracesetup": [
{ {
"clkMhz": "200", "clkMhz": 200,
"name": "ddr3_example.stl" "name": "ddr3_example.stl"
} }
] ]
} }
} }

4
DRAMSys/library/resources/simulations/hbm2-example.json
View File

@@ -8,9 +8,9 @@
"thermalconfig": "config.xml", "thermalconfig": "config.xml",
"tracesetup": [ "tracesetup": [
{ {
"clkMhz": "1000", "clkMhz": 1000,
"name": "ddr3_example.stl" "name": "ddr3_example.stl"
} }
] ]
} }
} }

4
DRAMSys/library/resources/simulations/lpddr4-example.json
View File

@@ -8,9 +8,9 @@
"thermalconfig": "config.xml", "thermalconfig": "config.xml",
"tracesetup": [ "tracesetup": [
{ {
"clkMhz": "200", "clkMhz": 200,
"name": "ddr3_example.stl" "name": "ddr3_example.stl"
} }
] ]
} }
} }

4
DRAMSys/library/resources/simulations/ranktest.json
View File

@@ -8,9 +8,9 @@
"thermalconfig": "config.xml", "thermalconfig": "config.xml",
"tracesetup": [ "tracesetup": [
{ {
"clkMhz": "200", "clkMhz": 200,
"name": "ranktest.stl" "name": "ranktest.stl"
} }
] ]
} }
} }

4
DRAMSys/library/resources/simulations/rgrsim.json
View File

@@ -8,9 +8,9 @@
"thermalconfig": "config.xml", "thermalconfig": "config.xml",
"tracesetup": [ "tracesetup": [
{ {
"clkMhz": "1000", "clkMhz": 1000,
"name": "1_720x1280_64-Pixelgroesse_imb3_str1_scram_ddr4_8b_same_clock.stl" "name": "1_720x1280_64-Pixelgroesse_imb3_str1_scram_ddr4_8b_same_clock.stl"
} }
] ]
} }
} }

8
DRAMSys/library/resources/simulations/sms-example.json
View File

@@ -8,17 +8,17 @@
"thermalconfig": "config.xml", "thermalconfig": "config.xml",
"tracesetup": [ "tracesetup": [
{ {
"clkMhz": "1000", "clkMhz": 1000,
"name": "random.stl" "name": "random.stl"
}, },
{ {
"clkMhz": "1000", "clkMhz": 1000,
"name": "chstone-adpcm_32.stl" "name": "chstone-adpcm_32.stl"
}, },
{ {
"clkMhz": "1000", "clkMhz": 1000,
"name": "stream.stl" "name": "stream.stl"
} }
] ]
} }
} }

4
DRAMSys/library/resources/simulations/wideio-ecc.json
View File

@@ -8,9 +8,9 @@
"thermalconfig": "config.xml", "thermalconfig": "config.xml",
"tracesetup": [ "tracesetup": [
{ {
"clkMhz": "1000", "clkMhz": 1000,
"name": "test_ecc.stl" "name": "test_ecc.stl"
} }
] ]
} }
} }

4
DRAMSys/library/resources/simulations/wideio-example.json
View File

@@ -8,9 +8,9 @@
"thermalconfig": "config.xml", "thermalconfig": "config.xml",
"tracesetup": [ "tracesetup": [
{ {
"clkMhz": "1000", "clkMhz": 1000,
"name": "chstone-adpcm_32.stl" "name": "chstone-adpcm_32.stl"
} }
] ]
} }
} }

52
DRAMSys/library/src/configuration/Configuration.cpp
View File

@@ -65,7 +65,7 @@ enum sc_time_unit string2TimeUnit(std::string s)
} }
} }
void Configuration::setParameter(std::string name, std::string value) void Configuration::setParameter(std::string name, nlohmann::json value)
{ {
// MCConfig // MCConfig
if (name == "PagePolicy") if (name == "PagePolicy")
@@ -73,7 +73,7 @@ void Configuration::setParameter(std::string name, std::string value)
else if (name == "Scheduler") else if (name == "Scheduler")
scheduler = value; scheduler = value;
else if (name == "RequestBufferSize") else if (name == "RequestBufferSize")
requestBufferSize = std::stoul(value); requestBufferSize = value;
else if (name == "CmdMux") else if (name == "CmdMux")
cmdMux = value; cmdMux = value;
else if (name == "RespQueue") else if (name == "RespQueue")
@@ -81,43 +81,43 @@ void Configuration::setParameter(std::string name, std::string value)
else if (name == "RefreshPolicy") else if (name == "RefreshPolicy")
refreshPolicy = value; refreshPolicy = value;
else if (name == "RefreshMode") else if (name == "RefreshMode")
refreshMode = std::stoul(value); refreshMode = value;
else if (name == "RefreshMaxPostponed") else if (name == "RefreshMaxPostponed")
refreshMaxPostponed = std::stoul(value); refreshMaxPostponed = value;
else if (name == "RefreshMaxPulledin") else if (name == "RefreshMaxPulledin")
refreshMaxPulledin = std::stoul(value); refreshMaxPulledin = value;
else if (name == "PowerDownPolicy") else if (name == "PowerDownPolicy")
powerDownPolicy = value; powerDownPolicy = value;
else if (name == "PowerDownTimeout") else if (name == "PowerDownTimeout")
powerDownTimeout = std::stoul(value); powerDownTimeout = value;
//SimConfig------------------------------------------------ //SimConfig------------------------------------------------
else if (name == "SimulationName") else if (name == "SimulationName")
simulationName = value; simulationName = value;
else if (name == "DatabaseRecording") else if (name == "DatabaseRecording")
databaseRecording = std::stoul(value); databaseRecording = value;
else if (name == "PowerAnalysis") else if (name == "PowerAnalysis")
powerAnalysis = std::stoul(value); powerAnalysis = value;
else if (name == "EnableWindowing") else if (name == "EnableWindowing")
enableWindowing = std::stoul(value); enableWindowing = value;
else if (name == "WindowSize") else if (name == "WindowSize")
{ {
windowSize = std::stoul(value); windowSize = value;
if (windowSize == 0) if (windowSize == 0)
SC_REPORT_FATAL("Configuration", SC_REPORT_FATAL("Configuration",
("Invalid value for parameter " + name + ("Invalid value for parameter " + name +
". This parameter must be at least one.").c_str()); ". This parameter must be at least one.").c_str());
} }
else if (name == "Debug") else if (name == "Debug")
debug = std::stoul(value); debug = value;
else if (name == "NumberOfMemChannels") else if (name == "NumberOfMemChannels")
numberOfMemChannels = std::stoul(value); numberOfMemChannels = value;
else if (name == "ThermalSimulation") else if (name == "ThermalSimulation")
thermalSimulation = std::stoul(value); thermalSimulation = value;
else if (name == "SimulationProgressBar") else if (name == "SimulationProgressBar")
simulationProgressBar = std::stoul(value); simulationProgressBar = value;
else if (name == "NumberOfDevicesOnDIMM") else if (name == "NumberOfDevicesOnDIMM")
{ {
numberOfDevicesOnDIMM = std::stoul(value); numberOfDevicesOnDIMM = value;
if (numberOfDevicesOnDIMM == 0) if (numberOfDevicesOnDIMM == 0)
SC_REPORT_FATAL("Configuration", SC_REPORT_FATAL("Configuration",
("Invalid value for parameter " + name + ("Invalid value for parameter " + name +
@@ -126,20 +126,20 @@ void Configuration::setParameter(std::string name, std::string value)
else if (name == "AddressOffset") else if (name == "AddressOffset")
{ {
#ifdef DRAMSYS_GEM5 #ifdef DRAMSYS_GEM5
addressOffset = std::stoull(value); addressOffset = value;
#else #else
addressOffset = 0; addressOffset = 0;
#endif #endif
} }
else if (name == "UseMalloc") else if (name == "UseMalloc")
useMalloc = std::stoul(value); useMalloc = value;
else if (name == "CheckTLM2Protocol") else if (name == "CheckTLM2Protocol")
checkTLM2Protocol = std::stoul(value); checkTLM2Protocol = value;
else if (name == "ECCControllerMode") else if (name == "ECCControllerMode")
ECCMode = value; ECCMode = value;
// Specification for ErrorChipSeed, ErrorCSVFile path and StoreMode // Specification for ErrorChipSeed, ErrorCSVFile path and StoreMode
else if (name == "ErrorChipSeed") else if (name == "ErrorChipSeed")
errorChipSeed = std::stoul(value); errorChipSeed = value;
else if (name == "ErrorCSVFile") else if (name == "ErrorCSVFile")
errorCSVFile = value; errorCSVFile = value;
else if (name == "StoreMode") else if (name == "StoreMode")
@@ -153,9 +153,9 @@ void Configuration::setParameter(std::string name, std::string value)
temperatureSim.TemperatureScale = value; temperatureSim.TemperatureScale = value;
} }
else if (name == "StaticTemperatureDefaultValue") else if (name == "StaticTemperatureDefaultValue")
temperatureSim.StaticTemperatureDefaultValue = std::stoi(value); temperatureSim.StaticTemperatureDefaultValue = value;
else if (name == "ThermalSimPeriod") else if (name == "ThermalSimPeriod")
temperatureSim.ThermalSimPeriod = std::stod(value.c_str()); temperatureSim.ThermalSimPeriod = value;
else if (name == "ThermalSimUnit") else if (name == "ThermalSimUnit")
temperatureSim.ThermalSimUnit = string2TimeUnit(value); temperatureSim.ThermalSimUnit = string2TimeUnit(value);
else if (name == "PowerInfoFile") else if (name == "PowerInfoFile")
@@ -166,15 +166,15 @@ void Configuration::setParameter(std::string name, std::string value)
else if (name == "IceServerIp") else if (name == "IceServerIp")
temperatureSim.IceServerIp = value; temperatureSim.IceServerIp = value;
else if (name == "IceServerPort") else if (name == "IceServerPort")
temperatureSim.IceServerPort = std::stoul(value); temperatureSim.IceServerPort = value;
else if (name == "SimPeriodAdjustFactor") else if (name == "SimPeriodAdjustFactor")
temperatureSim.SimPeriodAdjustFactor = std::stoi(value.c_str()); temperatureSim.SimPeriodAdjustFactor = value;
else if (name == "NPowStableCyclesToIncreasePeriod") else if (name == "NPowStableCyclesToIncreasePeriod")
temperatureSim.NPowStableCyclesToIncreasePeriod = std::stoi(value.c_str()); temperatureSim.NPowStableCyclesToIncreasePeriod = value;
else if (name == "GenerateTemperatureMap") else if (name == "GenerateTemperatureMap")
temperatureSim.GenerateTemperatureMap = std::stoul(value); temperatureSim.GenerateTemperatureMap = value;
else if (name == "GeneratePowerMap") else if (name == "GeneratePowerMap")
temperatureSim.GeneratePowerMap = std::stoul(value); temperatureSim.GeneratePowerMap = value;
else else
SC_REPORT_FATAL("Configuration", SC_REPORT_FATAL("Configuration",
("Parameter " + name + " not defined in Configuration").c_str()); ("Parameter " + name + " not defined in Configuration").c_str());

2
DRAMSys/library/src/configuration/Configuration.h
View File

@@ -91,7 +91,7 @@ struct Configuration
// MemSpec (from DRAM-Power) // MemSpec (from DRAM-Power)
MemSpec *memSpec; MemSpec *memSpec;
void setParameter(std::string name, std::string value); void setParameter(std::string name, nlohmann::json value);
//Configs for Seed, csv file and StorageMode //Configs for Seed, csv file and StorageMode
unsigned int errorChipSeed; unsigned int errorChipSeed;

7
DRAMSys/library/src/configuration/TemperatureSimConfig.h
View File

@@ -94,15 +94,14 @@ struct TemperatureSimConfig
// Load initial power values for all devices // Load initial power values for all devices
auto value= it.value(); auto value= it.value();
std::string init_pow_str = value["init_pow"]; float pow = value["init_pow"];
float pow = std::stof(init_pow_str);
powerInitialValues.push_back(pow); powerInitialValues.push_back(pow);
// Load power thresholds for all devices // Load power thresholds for all devices
//Changes in power dissipation that exceed the threshods //Changes in power dissipation that exceed the threshods
//will make the thermal simulation to be executed more often) //will make the thermal simulation to be executed more often)
std::string thr_str = value["threshold"];
float thr = std::stof(thr_str); float thr = value["threshold"];
powerThresholds.push_back(thr); powerThresholds.push_back(thr);
} }
} }

203
README.md
View File

@@ -115,13 +115,12 @@ The compilation generates executable binary files **DRAMSys** and
From the build directory use the commands below to execute DRAMSys. From the build directory use the commands below to execute DRAMSys.
```bash ```bash
$ cd simulator
$ ./DRAMSys $ ./DRAMSys
``` ```
To run DRAMSys with a specific config: To run DRAMSys with a specific config:
```bash ```bash
$ ./DRAMSys ../../DRAMSys/library/resources/simulations/ddr3-example.json $ ./DRAMSys ../DRAMSys/library/resources/simulations/ddr3-example.json
``` ```
To run DRAMSys with a specific config and a resource folder somewhere else to the standard: To run DRAMSys with a specific config and a resource folder somewhere else to the standard:
@@ -290,23 +289,23 @@ Below, the sub-configurations are listed and explained.
```json ```json
{ {
"simconfig": { "simconfig": {
"AddressOffset": "0", "AddressOffset": 0,
"CheckTLM2Protocol": "0", "CheckTLM2Protocol": false,
"DatabaseRecording": "1", "DatabaseRecording": true,
"Debug": "0", "Debug": false,
"ECCControllerMode": "Disabled", "ECCControllerMode": "Disabled",
"EnableWindowing": "0", "EnableWindowing": false,
"ErrorCSVFile": "", "ErrorCSVFile": "",
"ErrorChipSeed": "42", "ErrorChipSeed": 42,
"NumberOfDevicesOnDIMM": "8", "NumberOfDevicesOnDIMM": 8,
"NumberOfMemChannels": "1", "NumberOfMemChannels": 1,
"PowerAnalysis": "0", "PowerAnalysis": false,
"SimulationName": "ddr3", "SimulationName": "ddr3",
"SimulationProgressBar": "1", "SimulationProgressBar": true,
"StoreMode": "NoStorage", "StoreMode": "NoStorage",
"ThermalSimulation": "0", "ThermalSimulation": false,
"UseMalloc": "0", "UseMalloc": false,
"WindowSize": "1000" "WindowSize": 1000
} }
} }
``` ```
@@ -314,44 +313,44 @@ Below, the sub-configurations are listed and explained.
- *SimulationName* (boolean) - *SimulationName* (boolean)
- Give the name of the simulation for distingushing from other simulations. - Give the name of the simulation for distingushing from other simulations.
- *Debug* (boolean) - *Debug* (boolean)
- "1": enables debug output on console - true: enables debug output on console
- "0": disables debug output - false: disables debug output
- *DatabaseRecording* (boolean) - *DatabaseRecording* (boolean)
- "1": enables trace file recording for the trace analyser tool - true: enables trace file recording for the trace analyser tool
- "0": disables trace file recording - false: disables trace file recording
- *PowerAnalysis* (boolean) - *PowerAnalysis* (boolean)
- "1": enables live power analysis with the DRAMPower tool - true: enables live power analysis with the DRAMPower tool
- "0": disables power analysis - false: disables power analysis
- *EnableWindowing* (boolean) - *EnableWindowing* (boolean)
- "1": enables temporal windowing - true: enables temporal windowing
- "0": disables temporal windowing - false: disables temporal windowing
- *WindowSize* (unisgned int) - *WindowSize* (unisgned int)
- Size of the window in clock cycles used to evaluate average bandwidth and average power consumption - Size of the window in clock cycles used to evaluate average bandwidth and average power consumption
- *NumberOfMemChannels* (unsigned int) - *NumberOfMemChannels* (unsigned int)
- Number of memory channels - Number of memory channels
- *ControllerCoreRefDisable* (boolean) - *ControllerCoreRefDisable* (boolean)
- "1": disables refreshes - true: disables refreshes
- "0": normal operation (refreshes enabled) - false: normal operation (refreshes enabled)
- *ControllerCoreRGR* (boolean) - *ControllerCoreRGR* (boolean)
- "1": enable row granular refresh - true: enable row granular refresh
- "0": normal operation - false: normal operation
- *ThermalSimulation* (boolean) - *ThermalSimulation* (boolean)
- "1": enables thermal simulation - true: enables thermal simulation
- "0": static temperature during simulation - false: static temperature during simulation
- *SimulationProgressBar* (boolean) - *SimulationProgressBar* (boolean)
- "1": enables the simulation progress bar - true: enables the simulation progress bar
- "0": disables the simulation progress bar - false: disables the simulation progress bar
- *NumberOfDevicesOnDIMM* (unsigned int) - *NumberOfDevicesOnDIMM* (unsigned int)
- Number of devices on dual inline memory module - Number of devices on dual inline memory module
- *CheckTLM2Protocol* (boolean) - *CheckTLM2Protocol* (boolean)
- "1": enables the TLM-2.0 Protocol Checking - true: enables the TLM-2.0 Protocol Checking
- "0": disables the TLM-2.0 Protocol Checking - false: disables the TLM-2.0 Protocol Checking
- *ECCControllerMode* (string) - *ECCControllerMode* (string)
- "Disabled": No ECC Controller is used - "Disabled": No ECC Controller is used
- "Hamming": Enables an ECC Controller with classic SECDED implementation using Hamming Code - "Hamming": Enables an ECC Controller with classic SECDED implementation using Hamming Code
- *UseMalloc* (boolean) - *UseMalloc* (boolean)
- "0": model storage using mmap() (DEFAULT) - false: model storage using mmap() (DEFAULT)
- "1": allocate memory for modeling storage using malloc() - true: allocate memory for modeling storage using malloc()
- **Temperature Simulator Configuration** - **Temperature Simulator Configuration**
@@ -363,21 +362,19 @@ Below, the sub-configurations are listed and explained.
{ {
"thermalsimconfig": { "thermalsimconfig": {
"TemperatureScale": "Celsius", "TemperatureScale": "Celsius",
"StaticTemperatureDefaultValue": "89", "StaticTemperatureDefaultValue": 89,
"ThermalSimPeriod":"100", "ThermalSimPeriod":100,
"ThermalSimUnit":"us", "ThermalSimUnit":"us",
"PowerInfoFile": "powerInfo.json", "PowerInfoFile": "powerInfo.json",
"IceServerIp": "127.0.0.1", "IceServerIp": "127.0.0.1",
"IceServerPort": "11880", "IceServerPort": 11880,
"SimPeriodAdjustFactor" : "10", "SimPeriodAdjustFactor" : 10,
"NPowStableCyclesToIncreasePeriod": "5", "NPowStableCyclesToIncreasePeriod": 5,
"GenerateTemperatureMap": "1", "GenerateTemperatureMap": true,
"GeneratePowerMap": "1" "GeneratePowerMap": true
} }
} }
``` ```
The following types should be respected but written inside string quotes, not directly.
- *TemperatureScale* (string) - *TemperatureScale* (string)
- "Celsius" - "Celsius"
- "Fahrenheit" - "Fahrenheit"
@@ -404,11 +401,11 @@ Below, the sub-configurations are listed and explained.
- *NPowStableCyclesToIncreasePeriod* (unsigned int) - *NPowStableCyclesToIncreasePeriod* (unsigned int)
- Wait this number of thermal simulation cycles with power stability (i.e., changes that do not exceed the thresholds) to start increasing the simulation period back to its configured value. - Wait this number of thermal simulation cycles with power stability (i.e., changes that do not exceed the thresholds) to start increasing the simulation period back to its configured value.
- *GenerateTemperatureMap* (boolean) - *GenerateTemperatureMap* (boolean)
- "1": generate temperature map files during thermal simulation - true: generate temperature map files during thermal simulation
- "0": do not generate temperature map files during thermal simulation - false: do not generate temperature map files during thermal simulation
- *GeneratePowerMap* (boolean) - *GeneratePowerMap* (boolean)
- "1": generate power map files during thermal simulation - true: generate power map files during thermal simulation
- "0": do not generate power map files during thermal simulation - false: do not generate power map files during thermal simulation
- **Memory Specification** - **Memory Specification**
@@ -482,25 +479,25 @@ Below, the sub-configurations are listed and explained.
"mcconfig": { "mcconfig": {
"PagePolicy": "Open", "PagePolicy": "Open",
"Scheduler": "Fifo", "Scheduler": "Fifo",
"RequestBufferSize": "8", "RequestBufferSize": 8,
"CmdMux": "Oldest", "CmdMux": "Oldest",
"RespQueue": "Fifo", "RespQueue": "Fifo",
"RefreshPolicy": "Rankwise", "RefreshPolicy": "Rankwise",
"RefreshMode": "1", "RefreshMode": 1,
"RefreshMaxPostponed": "8", "RefreshMaxPostponed": 8,
"RefreshMaxPulledin": "8", "RefreshMaxPulledin": 8,
"PowerDownPolicy": "NoPowerDown", "PowerDownPolicy": "NoPowerDown",
"PowerDownTimeout": "100" "PowerDownTimeout": 100
} }
} }
``` ```
- *BankwiseLogic* (boolean) - *BankwiseLogic* (boolean)
- "1": perform bankwise-refresh [3] and bankwise-powerdown [4] - true: perform bankwise-refresh [3] and bankwise-powerdown [4]
- "0": do not perform bankwise operations - false: do not perform bankwise operations
- *OpenPagePolicy* (boolean) - *OpenPagePolicy* (boolean)
- "1": use open page precharge policy - true: use open page precharge policy
- "0": do not use open page precharge policy - false: do not use open page precharge policy
- *MaxNrOfTransactions* (unsigned int) - *MaxNrOfTransactions* (unsigned int)
- Maximum number of transactions. - Maximum number of transactions.
- *Scheduler* (string) - *Scheduler* (string)
@@ -519,11 +516,11 @@ Below, the sub-configurations are listed and explained.
- "TimeoutPDN": precharge idle - "TimeoutPDN": precharge idle
- "TimeoutSREF": self refresh - "TimeoutSREF": self refresh
- *ReadWriteGrouping* (boolean) - *ReadWriteGrouping* (boolean)
- "1": enable read writing grouping - true: enable read writing grouping
- "0": disable read writing grouping - false: disable read writing grouping
- *ReorderBuffer* (boolean) - *ReorderBuffer* (boolean)
- "1": use reordering buffer - true: use reordering buffer
- "0": do not use reordering buffer - false: do not use reordering buffer
- *ErrorChipSeed* (unsigned int) - *ErrorChipSeed* (unsigned int)
- Seed to initialize the random error generator. - Seed to initialize the random error generator.
- *ErrorCSVFile* (string) - *ErrorCSVFile* (string)
@@ -533,82 +530,82 @@ Below, the sub-configurations are listed and explained.
- "Store": store data without error model - "Store": store data without error model
- "ErrorModel": store data with error model [6] - "ErrorModel": store data with error model [6]
- *ControllerCoreRefDisable* (boolean) - *ControllerCoreRefDisable* (boolean)
- "1": disables refreshes - true: disables refreshes
- "0": normal operation (refreshes enabled) - false: normal operation (refreshes enabled)
- ControllerCoreRefMode (unsigned int) - ControllerCoreRefMode (unsigned int)
- Refresh mode. 1: 1X, 2: 2X, 4: 4X. Refresh period is tREFI, tREFI/2, - Refresh mode. 1: 1X, 2: 2X, 4: 4X. Refresh period is tREFI, tREFI/2,
tREFI/4, respectively. Number of rows per refresh is affected. Maximum tREFI/4, respectively. Number of rows per refresh is affected. Maximum
values for pull-in and postpone are affected. There are different values values for pull-in and postpone are affected. There are different values
of tRFC for each mode that come from memory specifications. of tRFC for each mode that come from memory specifications.
- *ControllerCoreRefForceMaxPostponeBurst* (boolean) - *ControllerCoreRefForceMaxPostponeBurst* (boolean)
- "1": always postpone, resulting in a ControllerCoreRefMaxPostponed burst - true: always postpone, resulting in a ControllerCoreRefMaxPostponed burst
- "0": normal operation - false: normal operation
- *ControllerCoreRefEnablePostpone* (boolean) - *ControllerCoreRefEnablePostpone* (boolean)
- "1": enables the postpone refresh feature - true: enables the postpone refresh feature
- "0": normal operation - false: normal operation
- *ControllerCoreRefEnablePullIn* (boolean) - *ControllerCoreRefEnablePullIn* (boolean)
- "1": enables the pull-in refresh feature - true: enables the pull-in refresh feature
- "0": normal operation - false: normal operation
- *ControllerCoreRefMaxPostponed* (unsigned int) - *ControllerCoreRefMaxPostponed* (unsigned int)
- Max AR commands to be postponed. Refresh mode affects this config. - Max AR commands to be postponed. Refresh mode affects this config.
- *ControllerCoreRefMaxPulledIn* (unsigned int) - *ControllerCoreRefMaxPulledIn* (unsigned int)
- Max AR commands to be pulled-in. Refresh mode affects this config. - Max AR commands to be pulled-in. Refresh mode affects this config.
- *ControllerCoreRGR* (boolean) - *ControllerCoreRGR* (boolean)
- "1": enables row granular refresh feature (RGR) - true: enables row granular refresh feature (RGR)
- "0": normal operation - false: normal operation
- *ControllerCoreRefNumARCmdsIntREFI* (unsigned int) - *ControllerCoreRefNumARCmdsIntREFI* (unsigned int)
- Number of AR commands to to be issued in a refresh period tREFI in 1X - Number of AR commands to to be issued in a refresh period tREFI in 1X
mode mode
- *ControllerCoreRGRRowInc* (unsigned int) - *ControllerCoreRGRRowInc* (unsigned int)
- Row increment for each AR command (selective refresh) - Row increment for each AR command (selective refresh)
- *ControllerCoreRGRB0* (boolean) - *ControllerCoreRGRB0* (boolean)
- "1": RGR this bank - true: RGR this bank
- "0": skip this bank - false: skip this bank
- *ControllerCoreRGRB1* (boolean) - *ControllerCoreRGRB1* (boolean)
- "1": RGR this bank - true: RGR this bank
- "0": skip this bank - false: skip this bank
- *ControllerCoreRGRB2* (boolean) - *ControllerCoreRGRB2* (boolean)
- "1": RGR this bank - true: RGR this bank
- "0": skip this bank - false: skip this bank
- *ControllerCoreRGRB3* (boolean) - *ControllerCoreRGRB3* (boolean)
- "1": RGR this bank - true: RGR this bank
- "0": skip this bank - false: skip this bank
- *ControllerCoreRGRB4* (boolean) - *ControllerCoreRGRB4* (boolean)
- "1": RGR this bank - true: RGR this bank
- "0": skip this bank - false: skip this bank
- *ControllerCoreRGRB5* (boolean) - *ControllerCoreRGRB5* (boolean)
- "1": RGR this bank - true: RGR this bank
- "0": skip this bank - false: skip this bank
- *ControllerCoreRGRB6* (boolean) - *ControllerCoreRGRB6* (boolean)
- "1": RGR this bank - true: RGR this bank
- "0": skip this bank - false: skip this bank
- *ControllerCoreRGRB7* (boolean) - *ControllerCoreRGRB7* (boolean)
- "1": RGR this bank - true: RGR this bank
- "0": skip this bank - false: skip this bank
- *ControllerCoreRGRB8* (boolean) - *ControllerCoreRGRB8* (boolean)
- "1": RGR this bank - true: RGR this bank
- "0": skip this bank - false: skip this bank
- *ControllerCoreRGRB9* (boolean) - *ControllerCoreRGRB9* (boolean)
- "1": RGR this bank - true: RGR this bank
- "0": skip this bank - false: skip this bank
- *ControllerCoreRGRB10* (boolean) - *ControllerCoreRGRB10* (boolean)
- "1": RGR this bank - true: RGR this bank
- "0": skip this bank - false: skip this bank
- *ControllerCoreRGRB11* (boolean) - *ControllerCoreRGRB11* (boolean)
- "1": RGR this bank - true: RGR this bank
- "0": skip this bank - false: skip this bank
- *ControllerCoreRGRB12* (boolean) - *ControllerCoreRGRB12* (boolean)
- "1": RGR this bank - true: RGR this bank
- "0": skip this bank - false: skip this bank
- *ControllerCoreRGRB13* (boolean) - *ControllerCoreRGRB13* (boolean)
- "1": RGR this bank - true: RGR this bank
- "0": skip this bank - false: skip this bank
- *ControllerCoreRGRB14* (boolean) - *ControllerCoreRGRB14* (boolean)
- "1": RGR this bank - true: RGR this bank
- "0": skip this bank - false: skip this bank
- *ControllerCoreRGRB15* (boolean) - *ControllerCoreRGRB15* (boolean)
- "1": RGR this bank - true: RGR this bank
- "0": skip this bank - false: skip this bank
- *ControllerCoreRGRtRASBInClkCycles* (unsigned int) - *ControllerCoreRGRtRASBInClkCycles* (unsigned int)
- Timing can be changed to explore optimum row granular refresh (ORGR) - Timing can be changed to explore optimum row granular refresh (ORGR)
- *ControllerCoreRGRtRRDB_LInClkCycles* (unsigned int) - *ControllerCoreRGRtRRDB_LInClkCycles* (unsigned int)