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simulation files examples and README updated

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This commit is contained in:
scorrea
2020-05-19 12:22:08 +02:00
parent c1b5e2d2dd
commit b6f9c27722
46 changed files with 503 additions and 798 deletions
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14
DRAMSys/library/resources/configs/thermalsim/config.xml
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<!-- Temperature Simulator Configuration (used for all simulation setups) -->
<thermalsimconfig>
<TemperatureScale value="Celsius" />
<StaticTemperatureDefaultValue value="89" />
<ThermalSimPeriod value="100" />
<ThermalSimUnit value="us" />
<PowerInfoFile value="powerInfo.xml"/>
<IceServerIp value="127.0.0.1" />
<IceServerPort value="11880" />
<SimPeriodAdjustFactor value="10" />
<NPowStableCyclesToIncreasePeriod value="5" />
<GenerateTemperatureMap value="1" />
<GeneratePowerMap value="1" />
</thermalsimconfig>

8
DRAMSys/library/resources/configs/thermalsim/powerInfo.xml
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@@ -1,8 +0,0 @@
<powerInfo>
<!-- Power information must be provided for all floor plan elements -->
<dram_die_channel0 init_pow="0" threshold="1.0" />
<dram_die_channel1 init_pow="0" threshold="1.0" />
<dram_die_channel2 init_pow="0" threshold="1.0" />
<dram_die_channel3 init_pow="0" threshold="1.0" />
</powerInfo>

10
DRAMSys/library/resources/simulations/ddr3-boot-linux.json Normal file
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@@ -0,0 +1,10 @@
{
"simulation": {
"addressmapping": "am_ddr3_8x1Gbx8_dimm_p1KB_rbc.xml",
"mcconfig": "fifoStrict.json",
"memspec": "MICRON_1Gb_DDR3-1600_8bit_G.json",
"simconfig": "ddr3_boot_linux.xml",
"simulationid": "ddr3-boot-linux",
"thermalconfig": "config.xml"
}
}

21
DRAMSys/library/resources/simulations/ddr3-boot-linux.xml
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@@ -1,21 +0,0 @@
<simulation>
<!-- Simulation file identifier -->
<simulationid id="ddr3-boot-linux"></simulationid>
<!-- Configuration for the DRAMSys Simulator -->
<simconfig src="ddr3_boot_linux.xml" />
<!-- Temperature Simulator Configuration -->
<thermalconfig src="config.xml" />
<!-- Memory Device Specification: Which Device is on the DDR3 DIMM -->
<memspec src="MICRON_1Gb_DDR3-1600_8bit_G.json"></memspec>
<!-- Addressmapping Configuration of the Memory Controller -->
<addressmapping src="am_ddr3_8x1Gbx8_dimm_p1KB_rbc.xml"></addressmapping>
<!-- Memory Controller Configuration: -->
<mcconfig src="fifoStrict.json"/>
<!--
The following trace setup is only used in standalone mode.
In library mode e.g. in Platform Architect the trace setup is ignored.
<tracesetup>
<device clkMhz="200">ddr3_example.stl</device>
</tracesetup>
-->
</simulation>

16
DRAMSys/library/resources/simulations/ddr3-ecc.json Normal file
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@@ -0,0 +1,16 @@
{
"simulation": {
"addressmapping": "am_ddr3_8x1Gbx8_dimm_p1KB_brc.xml",
"mcconfig": "fifo.xml",
"memspec": "MICRON_1Gb_DDR3-1600_8bit_G_less_refresh.json",
"simconfig": "ddr3_ecc.xml",
"simulationid": "ddr3-ecc",
"thermalconfig": "config.xml",
"tracesetup": [
{
"clkMhz": "1000",
"name": "test_ecc.stl"
}
]
}
}

24
DRAMSys/library/resources/simulations/ddr3-ecc.xml
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@@ -1,24 +0,0 @@
<simulation>
<!-- Simulation file identifier -->
<simulationid id="ddr3-ecc"></simulationid>
<!-- Configuration for the DRAMSys Simulator -->
<simconfig src="ddr3_ecc.xml" />
<!-- Temperature Simulator Configuration -->
<thermalconfig src="config.xml" />
<!-- Memory Device Specification: Which Device is used for Wide I/O -->
<memspec src="MICRON_1Gb_DDR3-1600_8bit_G_less_refresh.json"></memspec>
<!-- Addressmapping Configuration of the Memory Controller -->
<addressmapping src="am_ddr3_8x1Gbx8_dimm_p1KB_brc.xml"></addressmapping>
<!-- Memory Controller Configuration -->
<mcconfig src="fifo.xml"/>
<!--
The following trace setup is only used in standalone mode.
In library mode e.g. in Platform Architect the trace setup is ignored.
-->
<tracesetup>
<!--
This device mimics an processor running at 1 GHz.
-->
<device clkMhz="1000">test_ecc.stl</device>
</tracesetup>
</simulation>

28
DRAMSys/library/resources/simulations/ddr3-example.json
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@@ -1,14 +1,16 @@
{
"simulation": {
"simulationid": "ddr3-example-all-json",
"simconfig": "ddr3.json",
"thermalconfig": "config.json",
"memspec": "MICRON_1Gb_DDR3-1600_8bit_G.json",
"addressmapping": "congen_extended_solution.json",
"mcconfig":"fifoStrict.json",
"tracesetup": [{
"clkMhz": 800,
"name": "ddr3_example.stl"}
]
}
}
"simulation": {
"addressmapping": "congen_extended_solution.json",
"mcconfig": "fifoStrict.json",
"memspec": "MICRON_1Gb_DDR3-1600_8bit_G.json",
"simconfig": "ddr3.json",
"simulationid": "ddr3-example-all-json",
"thermalconfig": "config.json",
"tracesetup": [
{
"clkMhz": "800",
"name": "ddr3_example.stl"
}
]
}
}

25
DRAMSys/library/resources/simulations/ddr3-example.xml
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@@ -1,25 +0,0 @@
<simulation>
<!-- Simulation file identifier -->
<simulationid id="ddr3-example-all-json"></simulationid>
<!-- Configuration for the DRAMSys Simulator -->
<simconfig src="ddr3.json" />
<!-- Temperature Simulator Configuration -->
<thermalconfig src="config.json" />
<!-- Memory Device Specification: Which Device is on the DDR3 DIMM -->
<memspec src="MICRON_1Gb_DDR3-1600_8bit_G.json"></memspec>
<!-- Addressmapping Configuration of the Memory Controller -->
<addressmapping src="congen_extended_solution.json"></addressmapping>
<!-- Memory Controller Configuration: -->
<mcconfig src="fifoStrict.json"/>
<!--
The following trace setup is only used in standalone mode.
In library mode e.g. in Platform Architect the trace setup is ignored.
-->
<tracesetup>
<!--
This device mimics an image processing application
running on an FPGA with 200 Mhz.
-->
<device clkMhz="800">ddr3_example.stl</device>
</tracesetup>
</simulation>

20
DRAMSys/library/resources/simulations/ddr3-example2.json Normal file
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{
"simulation": {
"addressmapping": "am_ddr3_8x1Gbx8_dimm_p1KB_brc.xml",
"mcconfig": "fifoStrict.json",
"memspec": "MICRON_1Gb_DDR3-1600_8bit_G.json",
"simconfig": "ddr3.xml",
"simulationid": "ddr3-example2",
"thermalconfig": "config.xml",
"tracesetup": [
{
"clkMhz": "300",
"name": "ddr3_example.stl"
},
{
"clkMhz": "400",
"name": "ddr3_example.stl"
}
]
}
}

26
DRAMSys/library/resources/simulations/ddr3-example2.xml
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@@ -1,26 +0,0 @@
<simulation>
<!-- Simulation file identifier -->
<simulationid id="ddr3-example2"></simulationid>
<!-- Configuration for the DRAMSys Simulator -->
<simconfig src="ddr3.xml" />
<!-- Temperature Simulator Configuration -->
<thermalconfig src="config.xml" />
<!-- Memory Device Specification: Which Device is on the DDR3 DIMM -->
<memspec src="MICRON_1Gb_DDR3-1600_8bit_G.json"></memspec>
<!-- Addressmapping Configuration of the Memory Controller -->
<addressmapping src="am_ddr3_8x1Gbx8_dimm_p1KB_brc.xml"></addressmapping>
<!-- Memory Controller Configuration: -->
<mcconfig src="fifoStrict.json"/>
<!--
The following trace setup is only used in standalone mode.
In library mode e.g. in Platform Architect the trace setup is ignored.
-->
<tracesetup>
<!--
Two memory bus master devices, one running at 300 MHz and the
other at 400 MHz.
-->
<device clkMhz="300">ddr3_example.stl</device>
<device clkMhz="400">ddr3_example.stl</device>
</tracesetup>
</simulation>

10
DRAMSys/library/resources/simulations/ddr3-gem5-se.json Normal file
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@@ -0,0 +1,10 @@
{
"simulation": {
"addressmapping": "am_ddr3_8x1Gbx8_dimm_p1KB_brc.xml",
"mcconfig": "fifoStrict.json",
"memspec": "MICRON_1Gb_DDR3-1600_8bit_G.json",
"simconfig": "ddr3_gem5_se.xml",
"simulationid": "ddr3-gem5-se",
"thermalconfig": "config.xml"
}
}

21
DRAMSys/library/resources/simulations/ddr3-gem5-se.xml
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@@ -1,21 +0,0 @@
<simulation>
<!-- Simulation file identifier -->
<simulationid id="ddr3-gem5-se"></simulationid>
<!-- Configuration for the DRAMSys Simulator -->
<simconfig src="ddr3_gem5_se.xml" />
<!-- Temperature Simulator Configuration -->
<thermalconfig src="config.xml" />
<!-- Memory Device Specification: Which Device is on the DDR3 DIMM -->
<memspec src="MICRON_1Gb_DDR3-1600_8bit_G.json"></memspec>
<!-- Addressmapping Configuration of the Memory Controller -->
<addressmapping src="am_ddr3_8x1Gbx8_dimm_p1KB_brc.xml"></addressmapping>
<!-- Memory Controller Configuration: -->
<mcconfig src="fifoStrict.json"/>
<!--
The following trace setup is only used in standalone mode.
In library mode e.g. in Platform Architect the trace setup is ignored.
<tracesetup>
<device clkMhz="200">ddr3_example.stl</device>
</tracesetup>
-->
</simulation>

16
DRAMSys/library/resources/simulations/ddr3-single-device.json Normal file
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@@ -0,0 +1,16 @@
{
"simulation": {
"addressmapping": "am_ddr3_1Gbx8_p1KB_brc.xml",
"mcconfig": "fifoStrict.json",
"memspec": "MICRON_1Gb_DDR3-1600_8bit_G.json",
"simconfig": "ddr3-single-device.xml",
"simulationid": "ddr3-single-device",
"thermalconfig": "config.xml",
"tracesetup": [
{
"clkMhz": "200",
"name": "ddr3_single_dev_example.stl"
}
]
}
}

25
DRAMSys/library/resources/simulations/ddr3-single-device.xml
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@@ -1,25 +0,0 @@
<simulation>
<!-- Simulation file identifier -->
<simulationid id="ddr3-single-device"></simulationid>
<!-- Configuration for the DRAMSys Simulator -->
<simconfig src="ddr3-single-device.xml" />
<!-- Temperature Simulator Configuration -->
<thermalconfig src="config.xml" />
<!-- Memory Device Specification: Which Device is simulated -->
<memspec src="MICRON_1Gb_DDR3-1600_8bit_G.json"></memspec>
<!-- Addressmapping Configuration of the Memory Controller -->
<addressmapping src="am_ddr3_1Gbx8_p1KB_brc.xml"></addressmapping>
<!-- Memory Controller Configuration: -->
<mcconfig src="fifoStrict.json"/>
<!--
The following trace setup is only used in standalone mode.
In library mode e.g. in Platform Architect the trace setup is ignored.
-->
<tracesetup>
<!--
This device mimics an image processing application
running on an FPGA with 200 Mhz.
-->
<device clkMhz="200">ddr3_single_dev_example.stl</device>
</tracesetup>
</simulation>

16
DRAMSys/library/resources/simulations/ddr3_postpone_ref_test.json Normal file
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@@ -0,0 +1,16 @@
{
"simulation": {
"addressmapping": "am_ddr3_8x1Gbx8_dimm_p1KB_brc.xml",
"mcconfig": "fifoStrict.json",
"memspec": "MICRON_1Gb_DDR3-1600_8bit_G.json",
"simconfig": "ddr3.xml",
"simulationid": "ddr3_postpone_ref_test",
"thermalconfig": "config.xml",
"tracesetup": [
{
"clkMhz": "1000",
"name": "ddr3_postpone_ref_test_1.stl"
}
]
}
}

21
DRAMSys/library/resources/simulations/ddr3_postpone_ref_test.xml
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@@ -1,21 +0,0 @@
<simulation>
<!-- Simulation file identifier -->
<simulationid id="ddr3_postpone_ref_test"></simulationid>
<!-- Configuration for the DRAMSys Simulator -->
<simconfig src="ddr3.xml" />
<!-- Temperature Simulator Configuration -->
<thermalconfig src="config.xml" />
<!-- Memory Device Specification: Which Device is on the DDR3 DIMM -->
<memspec src="MICRON_1Gb_DDR3-1600_8bit_G.json"></memspec>
<!-- Addressmapping Configuration of the Memory Controller -->
<addressmapping src="am_ddr3_8x1Gbx8_dimm_p1KB_brc.xml"></addressmapping>
<!-- Memory Controller Configuration: -->
<mcconfig src="fifoStrict.json"/>
<!--
The following trace setup is only used in standalone mode.
In library mode e.g. in Platform Architect the trace setup is ignored.
-->
<tracesetup>
<device clkMhz="1000">ddr3_postpone_ref_test_1.stl</device>
</tracesetup>
</simulation>

16
DRAMSys/library/resources/simulations/ddr4-example.json Normal file
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{
"simulation": {
"addressmapping": "am_ddr4_8x4Gbx8_dimm_p1KB_brc.xml",
"mcconfig": "fifoStrict.json",
"memspec": "JEDEC_4Gb_DDR4-1866_8bit_A.json",
"simconfig": "ddr4.xml",
"simulationid": "ddr4-example",
"thermalconfig": "config.xml",
"tracesetup": [
{
"clkMhz": "200",
"name": "ddr3_example.stl"
}
]
}
}

25
DRAMSys/library/resources/simulations/ddr4-example.xml
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@@ -1,25 +0,0 @@
<simulation>
<!-- Simulation file identifier -->
<simulationid id="ddr4-example"></simulationid>
<!-- Configuration for the DRAMSys Simulator -->
<simconfig src="ddr4.xml" />
<!-- Temperature Simulator Configuration -->
<thermalconfig src="config.xml" />
<!-- Memory Device Specification: Which Device is on the DDR3 DIMM -->
<memspec src="JEDEC_4Gb_DDR4-1866_8bit_A.json"></memspec>
<!-- Addressmapping Configuration of the Memory Controller -->
<addressmapping src="am_ddr4_8x4Gbx8_dimm_p1KB_brc.xml"></addressmapping>
<!-- Memory Controller Configuration: -->
<mcconfig src="fifoStrict.json"/>
<!--
The following trace setup is only used in standalone mode.
In library mode e.g. in Platform Architect the trace setup is ignored.
-->
<tracesetup>
<!--
This device mimics an image processing application
running on an FPGA with 200 Mhz.
-->
<device clkMhz="200">ddr3_example.stl</device>
</tracesetup>
</simulation>

16
DRAMSys/library/resources/simulations/hbm2-example.json Normal file
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@@ -0,0 +1,16 @@
{
"simulation": {
"addressmapping": "am_hbm2_8Gb_pc_brc.xml",
"mcconfig": "fifoStrict.json",
"memspec": "HBM2.json",
"simconfig": "hbm2.xml",
"simulationid": "hbm2-example",
"thermalconfig": "config.xml",
"tracesetup": [
{
"clkMhz": "1000",
"name": "ddr3_example.stl"
}
]
}
}

25
DRAMSys/library/resources/simulations/hbm2-example.xml
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@@ -1,25 +0,0 @@
<simulation>
<!-- Simulation file identifier -->
<simulationid id="hbm2-example"></simulationid>
<!-- Configuration for the DRAMSys Simulator -->
<simconfig src="hbm2.xml" />
<!-- Temperature Simulator Configuration -->
<thermalconfig src="config.xml" />
<!-- Memory Device Specification: Which Device is on the DDR3 DIMM -->
<memspec src="HBM2.json"></memspec>
<!-- Addressmapping Configuration of the Memory Controller -->
<addressmapping src="am_hbm2_8Gb_pc_brc.xml"></addressmapping>
<!-- Memory Controller Configuration: -->
<mcconfig src="fifoStrict.json"/>
<!--
The following trace setup is only used in standalone mode.
In library mode e.g. in Platform Architect the trace setup is ignored.
-->
<tracesetup>
<!--
This device mimics an image processing application
running on an FPGA with 200 Mhz.
-->
<device clkMhz="1000">ddr3_example.stl</device>
</tracesetup>
</simulation>

16
DRAMSys/library/resources/simulations/lpddr4-example.json Normal file
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@@ -0,0 +1,16 @@
{
"simulation": {
"addressmapping": "am_lpddr4_8Gbx16_brc.xml",
"mcconfig": "fifoStrict.json",
"memspec": "JEDEC_8Gb_LPDDR4-3200_16bit.json",
"simconfig": "lpddr4.xml",
"simulationid": "lpddr4-example",
"thermalconfig": "config.xml",
"tracesetup": [
{
"clkMhz": "200",
"name": "ddr3_example.stl"
}
]
}
}

25
DRAMSys/library/resources/simulations/lpddr4-example.xml
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@@ -1,25 +0,0 @@
<simulation>
<!-- Simulation file identifier -->
<simulationid id="lpddr4-example"></simulationid>
<!-- Configuration for the DRAMSys Simulator -->
<simconfig src="lpddr4.xml" />
<!-- Temperature Simulator Configuration -->
<thermalconfig src="config.xml" />
<!-- Memory Device Specification: Which Device is on the DDR3 DIMM -->
<memspec src="JEDEC_8Gb_LPDDR4-3200_16bit.json"></memspec>
<!-- Addressmapping Configuration of the Memory Controller -->
<addressmapping src="am_lpddr4_8Gbx16_brc.xml"></addressmapping>
<!-- Memory Controller Configuration: -->
<mcconfig src="fifoStrict.json"/>
<!--
The following trace setup is only used in standalone mode.
In library mode e.g. in Platform Architect the trace setup is ignored.
-->
<tracesetup>
<!--
This device mimics an image processing application
running on an FPGA with 200 Mhz.
-->
<device clkMhz="200">ddr3_example.stl</device>
</tracesetup>
</simulation>

16
DRAMSys/library/resources/simulations/ranktest.json Normal file
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@@ -0,0 +1,16 @@
{
"simulation": {
"addressmapping": "am_ranktest.xml",
"mcconfig": "fifoStrict.json",
"memspec": "memspec_ranktest.json",
"simconfig": "ddr3.xml",
"simulationid": "ranktest",
"thermalconfig": "config.xml",
"tracesetup": [
{
"clkMhz": "200",
"name": "ranktest.stl"
}
]
}
}

25
DRAMSys/library/resources/simulations/ranktest.xml
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@@ -1,25 +0,0 @@
<simulation>
<!-- Simulation file identifier -->
<simulationid id="ranktest"></simulationid>
<!-- Configuration for the DRAMSys Simulator -->
<simconfig src="ddr3.xml" />
<!-- Temperature Simulator Configuration -->
<thermalconfig src="config.xml" />
<!-- Memory Device Specification: Which Device is on the DDR3 DIMM -->
<memspec src="memspec_ranktest.json"></memspec>
<!-- Addressmapping Configuration of the Memory Controller -->
<addressmapping src="am_ranktest.xml"></addressmapping>
<!-- Memory Controller Configuration: -->
<mcconfig src="fifoStrict.json"/>
<!--
The following trace setup is only used in standalone mode.
In library mode e.g. in Platform Architect the trace setup is ignored.
-->
<tracesetup>
<!--
This device mimics an image processing application
running on an FPGA with 200 Mhz.
-->
<device clkMhz="200">ranktest.stl</device>
</tracesetup>
</simulation>

10
DRAMSys/library/resources/simulations/rgrsim-gem5-fs.json Normal file
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@@ -0,0 +1,10 @@
{
"simulation": {
"addressmapping": "rgram.xml",
"mcconfig": "rgrmccfg.xml",
"memspec": "rgrspec.json",
"simconfig": "rgrsimcfg-gem5-fs.xml",
"simulationid": "rgrsim-gem5-fs",
"thermalconfig": "config.xml"
}
}

20
DRAMSys/library/resources/simulations/rgrsim-gem5-fs.xml
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@@ -1,20 +0,0 @@
<simulation>
<!-- Simulation file identifier -->
<simulationid id="rgrsim-gem5-fs"></simulationid>
<!-- Configuration for the DRAMSys Simulator -->
<simconfig src="rgrsimcfg-gem5-fs.xml" />
<!-- Temperature Simulator Configuration -->
<thermalconfig src="config.xml" />
<!-- Memory Device Specification -->
<memspec src="rgrspec.json"></memspec>
<!-- Addressmapping Configuration of the Memory Controller -->
<addressmapping src="rgram.xml"></addressmapping>
<!-- Memory Controller Configuration -->
<mcconfig src="rgrmccfg.xml"/>
<!-- <tracesetup id="no_refresh_fr_fcfs_nbw_b16_ddr4_8b_1x"> -->
<!--
<tracesetup id="rgrsetup">
<device clkMhz="1000">1_720x1280_64-Pixelgroesse_imb3_str1_scram_ddr4_8b_same_clock.stl</device>
</tracesetup>
-->
</simulation>

10
DRAMSys/library/resources/simulations/rgrsim-gem5-se.json Normal file
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@@ -0,0 +1,10 @@
{
"simulation": {
"addressmapping": "rgram.xml",
"mcconfig": "rgrmccfg.xml",
"memspec": "rgrspec.json",
"simconfig": "rgrsimcfg-gem5-se.xml",
"simulationid": "rgrsim-gem5-se",
"thermalconfig": "config.xml"
}
}

20
DRAMSys/library/resources/simulations/rgrsim-gem5-se.xml
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@@ -1,20 +0,0 @@
<simulation>
<!-- Simulation file identifier -->
<simulationid id="rgrsim-gem5-se"></simulationid>
<!-- Configuration for the DRAMSys Simulator -->
<simconfig src="rgrsimcfg-gem5-se.xml" />
<!-- Temperature Simulator Configuration -->
<thermalconfig src="config.xml" />
<!-- Memory Device Specification -->
<memspec src="rgrspec.json"></memspec>
<!-- Addressmapping Configuration of the Memory Controller -->
<addressmapping src="rgram.xml"></addressmapping>
<!-- Memory Controller Configuration -->
<mcconfig src="rgrmccfg.xml"/>
<!-- <tracesetup id="no_refresh_fr_fcfs_nbw_b16_ddr4_8b_1x"> -->
<!--
<tracesetup id="rgrsetup">
<device clkMhz="1000">1_720x1280_64-Pixelgroesse_imb3_str1_scram_ddr4_8b_same_clock.stl</device>
</tracesetup>
-->
</simulation>

16
DRAMSys/library/resources/simulations/rgrsim.json Normal file
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@@ -0,0 +1,16 @@
{
"simulation": {
"addressmapping": "rgram.xml",
"mcconfig": "rgrmccfg.xml",
"memspec": "rgrspec.json",
"simconfig": "rgrsimcfg.xml",
"simulationid": "rgrsimid",
"thermalconfig": "config.xml",
"tracesetup": [
{
"clkMhz": "1000",
"name": "1_720x1280_64-Pixelgroesse_imb3_str1_scram_ddr4_8b_same_clock.stl"
}
]
}
}

18
DRAMSys/library/resources/simulations/rgrsim.xml
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@@ -1,18 +0,0 @@
<simulation>
<!-- Simulation file identifier -->
<simulationid id="rgrsimid"></simulationid>
<!-- Configuration for the DRAMSys Simulator -->
<simconfig src="rgrsimcfg.xml" />
<!-- Temperature Simulator Configuration -->
<thermalconfig src="config.xml" />
<!-- Memory Device Specification -->
<memspec src="rgrspec.json"></memspec>
<!-- Addressmapping Configuration of the Memory Controller -->
<addressmapping src="rgram.xml"></addressmapping>
<!-- Memory Controller Configuration -->
<mcconfig src="rgrmccfg.xml"/>
<!-- <tracesetup id="no_refresh_fr_fcfs_nbw_b16_ddr4_8b_1x"> -->
<tracesetup id="rgrsetup">
<device clkMhz="1000">1_720x1280_64-Pixelgroesse_imb3_str1_scram_ddr4_8b_same_clock.stl</device>
</tracesetup>
</simulation>

24
DRAMSys/library/resources/simulations/sms-example.json Normal file
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@@ -0,0 +1,24 @@
{
"simulation": {
"addressmapping": "am_wideio.xml",
"mcconfig": "sms.xml",
"memspec": "wideio.json",
"simconfig": "sms.xml",
"simulationid": "sms-example",
"thermalconfig": "config.xml",
"tracesetup": [
{
"clkMhz": "1000",
"name": "random.stl"
},
{
"clkMhz": "1000",
"name": "chstone-adpcm_32.stl"
},
{
"clkMhz": "1000",
"name": "stream.stl"
}
]
}
}

29
DRAMSys/library/resources/simulations/sms-example.xml
View File

@@ -1,29 +0,0 @@
<simulation>
<!-- Simulation file identifier -->
<simulationid id="sms-example"></simulationid>
<!-- General Simulator Configuration (used for all simulation setups) -->
<simconfig src="sms.xml" />
<!-- Temperature Simulator Configuration (used for all simulation setups) -->
<thermalconfig src="config.xml" />
<memspec src="wideio.json"></memspec>
<addressmapping src="am_wideio.xml"></addressmapping>
<mcconfig src="sms.xml"/>
<tracesetup id="sms">
<!-- <device clkMhz="200">ddr3_example.stl</device>
<device clkMhz="200">sms_t1.stl</device>
<device clkMhz="200">sms_t2.stl</device>
<device clkMhz="200">sms_t3.stl</device>
<device clkMhz="200">sms_t4.stl</device>-->
<device clkMhz="1000">random.stl</device>
<device clkMhz="1000">chstone-adpcm_32.stl</device>
<device clkMhz="1000">stream.stl</device>
</tracesetup>
</simulation>

16
DRAMSys/library/resources/simulations/wideio-ecc.json Normal file
View File

@@ -0,0 +1,16 @@
{
"simulation": {
"addressmapping": "am_wideio.xml",
"mcconfig": "fifo.json",
"memspec": "wideio_less_refresh.json",
"simconfig": "wideio_ecc.xml",
"simulationid": "wideio-ecc",
"thermalconfig": "config.xml",
"tracesetup": [
{
"clkMhz": "1000",
"name": "test_ecc.stl"
}
]
}
}

24
DRAMSys/library/resources/simulations/wideio-ecc.xml
View File

@@ -1,24 +0,0 @@
<simulation>
<!-- Simulation file identifier -->
<simulationid id="wideio-ecc"></simulationid>
<!-- Configuration for the DRAMSys Simulator -->
<simconfig src="wideio_ecc.xml" />
<!-- Temperature Simulator Configuration -->
<thermalconfig src="config.xml" />
<!-- Memory Device Specification: Which Device is used for Wide I/O -->
<memspec src="wideio_less_refresh.json"></memspec>
<!-- Addressmapping Configuration of the Memory Controller -->
<addressmapping src="am_wideio.xml"></addressmapping>
<!-- Memory Controller Configuration -->
<mcconfig src="fifo.json"/>
<!--
The following trace setup is only used in standalone mode.
In library mode e.g. in Platform Architect the trace setup is ignored.
-->
<tracesetup>
<!--
This device mimics an processor running at 1 GHz.
-->
<device clkMhz="1000">test_ecc.stl</device>
</tracesetup>
</simulation>

16
DRAMSys/library/resources/simulations/wideio-example.json Normal file
View File

@@ -0,0 +1,16 @@
{
"simulation": {
"addressmapping": "am_wideio.xml",
"mcconfig": "fifoStrict.json",
"memspec": "wideio.json",
"simconfig": "wideio.xml",
"simulationid": "wideio-example",
"thermalconfig": "config.xml",
"tracesetup": [
{
"clkMhz": "1000",
"name": "chstone-adpcm_32.stl"
}
]
}
}

24
DRAMSys/library/resources/simulations/wideio-example.xml
View File

@@ -1,24 +0,0 @@
<simulation>
<!-- Simulation file identifier -->
<simulationid id="wideio-example"></simulationid>
<!-- Configuration for the DRAMSys Simulator -->
<simconfig src="wideio.xml" />
<!-- Temperature Simulator Configuration -->
<thermalconfig src="config.xml" />
<!-- Memory Device Specification: Which Device is used for Wide I/O -->
<memspec src="wideio.json"></memspec>
<!-- Addressmapping Configuration of the Memory Controller -->
<addressmapping src="am_wideio.xml"></addressmapping>
<!-- Memory Controller Configuration -->
<mcconfig src="fifoStrict.json"/>
<!--
The following trace setup is only used in standalone mode.
In library mode e.g. in Platform Architect the trace setup is ignored.
-->
<tracesetup>
<!--
This device mimics an processor running at 1 GHz.
-->
<device clkMhz="1000">chstone-adpcm_32.stl</device>
</tracesetup>
</simulation>

2
DRAMSys/library/src/common/AddressDecoder.cpp
View File

@@ -48,7 +48,7 @@ unsigned int AddressDecoder::getUnsignedAttrFromJson(nlohmann::json obj, std::st
AddressDecoder::AddressDecoder(std::string pathToAddressMapping)
{
json AddrFile = json::parse(std::ifstream(pathToAddressMapping));
json AddrFile = parseJSON(pathToAddressMapping);
json j;
if (AddrFile["CONGEN"].empty())
reportFatal("AddressDecorder",

15
DRAMSys/library/src/common/utils.cpp
View File

@@ -138,6 +138,21 @@ std::string loadTextFileContents(std::string filename)
}
}
nlohmann::json parseJSON(std::string path){
try
{
// parsing input with a syntax error
nlohmann::json j = nlohmann::json::parse(std::ifstream(path));
return j;
}
catch (nlohmann::json::parse_error& e)
{
// output exception information
std::cout << "Error while trying to parse file: " << path << '\n'
<< "message: " << e.what() << std::endl;
}
}
void setUpDummy(tlm_generic_payload &payload, Rank rank, Bank bank)
{
payload.set_address(bank.getStartAddress());

4
DRAMSys/library/src/common/utils.h
View File

@@ -45,6 +45,8 @@
#include <tlm.h>
#include <iomanip>
#include "dramExtensions.h"
#include <fstream>
#include <sstream>
#include "../common/third_party/nlohmann/single_include/nlohmann/json.hpp"
#define DEF_SINGLETON( NAME ) \
@@ -144,6 +146,8 @@ unsigned int uIntParameter(nlohmann::json obj, std::string name);
double doubleParameter(nlohmann::json obj, std::string name);
std::string stringParameter(nlohmann::json obj);
nlohmann::json parseJSON(std::string path);
void setUpDummy(tlm::tlm_generic_payload &payload, Rank rank = Rank(0), Bank bank = Bank(0));
#endif // UTILS_H

18
DRAMSys/library/src/configuration/ConfigurationLoader.cpp
View File

@@ -36,16 +36,6 @@
*/
#include "ConfigurationLoader.h"
#include "memspec/MemSpec.h"
#include "memspec/MemSpecDDR3.h"
#include "memspec/MemSpecDDR4.h"
#include "memspec/MemSpecWideIO.h"
#include "memspec/MemSpecLPDDR4.h"
#include "memspec/MemSpecWideIO2.h"
#include "memspec/MemSpecHBM2.h"
#include "memspec/MemSpecGDDR5.h"
#include "memspec/MemSpecGDDR5X.h"
#include "memspec/MemSpecGDDR6.h"
using json = nlohmann::json;
@@ -53,7 +43,7 @@ void ConfigurationLoader::loadSimConfig(Configuration &config,
std::string simconfigUri)
{
json doc = json::parse(std::ifstream(simconfigUri));
json doc = parseJSON(simconfigUri);
auto simconfig = doc["simconfig"].get_ptr<json::object_t*>();
loadConfigJson(config, simconfig);
}
@@ -62,7 +52,7 @@ void ConfigurationLoader::loadSimConfig(Configuration &config,
void ConfigurationLoader::loadTemperatureSimConfig(Configuration &config,
std::string thermalsimconfigUri)
{
json doc = json::parse(std::ifstream(thermalsimconfigUri));
json doc = parseJSON(thermalsimconfigUri);
auto thermalconfig = doc["thermalsimconfig"].get_ptr<json::object_t*>();
loadConfigJson(config, thermalconfig);
@@ -83,7 +73,7 @@ void ConfigurationLoader::loadMCConfig(Configuration &config,
std::string mcconfigUri)
{
config.mcconfigUri = mcconfigUri;
json doc = json::parse(std::ifstream(mcconfigUri));
json doc = parseJSON(mcconfigUri);
auto mcconfig = doc["mcconfig"].get_ptr<json::object_t*>();
loadConfigJson(config, mcconfig);
}
@@ -92,7 +82,7 @@ void ConfigurationLoader::loadMCConfig(Configuration &config,
void ConfigurationLoader::loadMemSpec(Configuration &config, std::string memspecUri)
{
config.memspecUri = memspecUri;
json doc = json::parse(std::ifstream(memspecUri));
json doc = parseJSON(memspecUri);
auto memspec = doc["memspec"].get_ptr<json::object_t*>();
loadMemSpec(config, memspec);
}

10
DRAMSys/library/src/configuration/ConfigurationLoader.h
View File

@@ -42,6 +42,16 @@
#include "../common/third_party/nlohmann/single_include/nlohmann/json.hpp"
#include "../common/utils.h"
#include "Configuration.h"
#include "memspec/MemSpec.h"
#include "memspec/MemSpecDDR3.h"
#include "memspec/MemSpecDDR4.h"
#include "memspec/MemSpecWideIO.h"
#include "memspec/MemSpecLPDDR4.h"
#include "memspec/MemSpecWideIO2.h"
#include "memspec/MemSpecHBM2.h"
#include "memspec/MemSpecGDDR5.h"
#include "memspec/MemSpecGDDR5X.h"
#include "memspec/MemSpecGDDR6.h"
class ConfigurationLoader
{

2
DRAMSys/library/src/configuration/TemperatureSimConfig.h
View File

@@ -81,7 +81,7 @@ struct TemperatureSimConfig
+ powerInfoFile;
// Load the JSON file into memory and parse it
nlohmann::json powInfoElem = nlohmann::json::parse(std::ifstream(powerInfoFile));
nlohmann::json powInfoElem = parseJSON(powerInfoFile);
if (powInfoElem["powerInfo"].empty()){
// Invalid file

2
DRAMSys/library/src/simulation/DRAMSys.cpp
View File

@@ -119,7 +119,7 @@ DRAMSys::DRAMSys(sc_module_name name,
std::string simName;
simName = Configuration::getInstance().simulationName;
nlohmann::json simulationdoc = nlohmann::json::parse(std::ifstream(simulationToRun));
nlohmann::json simulationdoc = parseJSON(simulationToRun);
if (!simulationdoc["simulation"]["simulationid"].empty()) {
std::string sid = simulationdoc["simulation"]["simulationid"];

2
DRAMSys/library/src/simulation/Setup.cpp
View File

@@ -44,7 +44,7 @@ Setup::Setup(std::string uri,
{
// Load Simulation:
nlohmann::json simulationdoc = nlohmann::json::parse(std::ifstream(uri));
nlohmann::json simulationdoc = parseJSON(uri);
if (simulationdoc["simulation"].empty())
reportFatal("SimulationManager",

2
DRAMSys/library/src/simulation/TraceSetup.cpp
View File

@@ -40,7 +40,7 @@ TraceSetup::TraceSetup(std::string uri,
std::vector<TracePlayer *> *devices)
{
// Load Simulation:
nlohmann::json simulationdoc = nlohmann::json::parse(std::ifstream(uri));
nlohmann::json simulationdoc = parseJSON(uri);
if (simulationdoc["simulation"].empty())

552
README.md
View File

@@ -121,12 +121,12 @@ $ ./DRAMSys
To run DRAMSys with a specific config:
```bash
$ ./DRAMSys ../../DRAMSys/library/resources/simulations/ddr3-example.xml
$ ./DRAMSys ../../DRAMSys/library/resources/simulations/ddr3-example.json
```
To run DRAMSys with a specific config and a resource folder somewhere else to the standard:
```bash
$ ./DRAMSys ../../DRAMSys/tests/example_ddr3/simulations/ddr3-example.xml ../../DRAMSys/tests/example_ddr3/
$ ./DRAMSys ../../DRAMSys/tests/example_ddr3/simulations/ddr3-example.json ../../DRAMSys/tests/example_ddr3/
```
From the build directory use the commands below to execute the traceAnalyzer.
@@ -175,50 +175,54 @@ section.
### DRAMSys Configuration
The **DRAMSys** executable supports one argument which is a XML file that
contains configurable aspects of the desired simulation. If no argument is
passed through the command line a default configuration file will be loaded.
The **DRAMSys** executable supports one argument which is a JSON file that
contains certain arguments and the path of other configuration files for the
desired simulation. If no argument is passed through the command line a default
configuration file will be loaded.
The XML code below shows a typic configuration:
The JSON code below shows a typic configuration:
```xml
<simulation>
<!-- Simulation file identifier -->
<simulationid id="ddr3-example"></simulationid>
<!-- Configuration for the DRAMSys Simulator -->
<simconfig src="ddr3.xml" />
<!-- Temperature Simulator Configuration -->
<thermalconfig src="config.xml" />
<!-- Memory Device Specification: Which Device is on the DDR3 DIMM -->
<memspec src="MICRON_1Gb_DDR3-1600_8bit_G.xml"></memspec>
<!-- Addressmapping Configuration of the Memory Controller -->
<addressmapping src="am_ddr3_8x1Gbx8_dimm_p1KB_brc.xml"></addressmapping>
<!-- Memory Controller Configuration: -->
<mcconfig src="fifoStrict.xml"/>
<!--
The following trace setup is only used in standalone mode.
In library mode e.g. in Platform Architect the trace setup is ignored.
-->
<tracesetup>
<!--
Specify here a trace file for each of the trace players. Trace
players without a file will not generate transactions.
-->
<device clkMhz="200">ddr3_example.stl</device>
<device clkMhz="100">ddr3_SAMSUNG_M471B5674QH0_DIMM_example.stl</device>
</tracesetup>
</simulation>
```json
{
"simulation": {
"simulationid": "ddr3-example2-id",
"simconfig": "ddr3.json",
"thermalconfig": "config.json",
"memspec": "MICRON_1Gb_DDR3-1600_8bit_G.json",
"addressmapping": "congen_extended_solution.json",
"mcconfig":"fifoStrict.json",
"tracesetup": [{
"clkMhz": 300,
"name": "ddr3_example.stl"},
{
"clkMhz": 400,
"name": "ddr3_example.stl"}
]
}
}
```
Some configuration fields reference other XML files which contain more
Fields Description
"simulationid": Simulation file identifier
"simconfig": Configuration file for the DRAMSys Simulator
"thermalconfig": Temperature Simulator Configuration File
"memspec": Memory Device Specification File
"addressmapping":Addressmapping Configuration of the Memory Controller File.
"mcconfig": Memory Controller Configuration File.
"tracesetup": The trace setup is only used in standalone mode.
In library mode e.g. in Platform Architect the trace setup is ignored.
Each device should be addes as a json object inside the "tracesetup" array.
Each **tracesetup** device configuration consists of two parameters - clkMhz
(operation frequency for this device) - and a **trace file**.
Some configuration fields reference other JSON files which contain more
specialized chunks of the configuration like memory specification, address
mapping and memory configurations
The XML configuration files are parsed by the program and the configuration
The JSON configuration files are parsed by the program and the configuration
details extracted are assigned to the correspondent attributes of the internal
configuration structure.
The **device** configuration consists of two parameters - clkMhz
(operation frequency for this device) - and a **trace file**.
#### Trace files
@@ -280,25 +284,32 @@ Below, the sub-configurations are listed and explained.
- **Simulator Configuration**
The content of
[ddr3.xml](DRAMSys/library/resources/configs/simulator/ddr3.xml) is
[ddr3.json](DRAMSys/library/resources/configs/simulator/ddr3.json) is
presented below as an example.
```xml
<simconfig>
<SimulationName value="ddr3" />
<Debug value="0" />
<DatabaseRecording value="1" />
<PowerAnalysis value="1" />
<EnableWindowing value = "1" />
<WindowSize value="100" />
<ThermalSimulation value="0"/>
<SimulationProgressBar value="1"/>
<NumberOfMemChannels value="1"/>
<NumberOfDevicesOnDIMM value = "8" />
<ECCControllerMode value = "Disabled" />
<UseMalloc value = "0" />
</simconfig>
```
```json
{
"simconfig": {
"AddressOffset": "0",
"CheckTLM2Protocol": "0",
"DatabaseRecording": "1",
"Debug": "0",
"ECCControllerMode": "Disabled",
"EnableWindowing": "0",
"ErrorCSVFile": "",
"ErrorChipSeed": "42",
"NumberOfDevicesOnDIMM": "8",
"NumberOfMemChannels": "1",
"PowerAnalysis": "0",
"SimulationName": "ddr3",
"SimulationProgressBar": "1",
"StoreMode": "NoStorage",
"ThermalSimulation": "0",
"UseMalloc": "0",
"WindowSize": "1000"
}
}
```
- *SimulationName* (boolean)
- Give the name of the simulation for distingushing from other simulations.
@@ -345,24 +356,27 @@ Below, the sub-configurations are listed and explained.
- **Temperature Simulator Configuration**
The content of
[config.xml](DRAMSys/library/resources/configs/thermalsim/config.xml) is
[config.json](DRAMSys/library/resources/configs/thermalsim/config.json) is
presented below as an example.
```xml
<thermalsimconfig>
<TemperatureScale value="Celsius" />
<StaticTemperatureDefaultValue value="89" />
<ThermalSimPeriod value="100" />
<ThermalSimUnit value="us" />
<PowerInfoFile value="../../DRAMSys/library/resources/configs/thermalsim/powerInfo.xml"/>
<IceServerIp value="127.0.0.1" />
<IceServerPort value="11880" />
<SimPeriodAdjustFactor value="10" />
<NPowStableCyclesToIncreasePeriod value="5" />
<GenerateTemperatureMap value="1" />
<GeneratePowerMap value="1" />
</thermalsimconfig>
```json
{
"thermalsimconfig": {
"TemperatureScale": "Celsius",
"StaticTemperatureDefaultValue": "89",
"ThermalSimPeriod":"100",
"ThermalSimUnit":"us",
"PowerInfoFile": "powerInfo.json",
"IceServerIp": "127.0.0.1",
"IceServerPort": "11880",
"SimPeriodAdjustFactor" : "10",
"NPowStableCyclesToIncreasePeriod": "5",
"GenerateTemperatureMap": "1",
"GeneratePowerMap": "1"
}
}
```
The following types should be respected but written inside string quotes, not directly.
- *TemperatureScale* (string)
- "Celsius"
@@ -401,76 +415,16 @@ Below, the sub-configurations are listed and explained.
A file with memory specifications. This information comes from datasheets and
measurements, and usually does not change.
The fields inside "mempowerspec" can be written directly as a **double** type. "memoryId" and "memoryType" are **string**. The others are **unsigned int** as it can be checked in the files at <DRAMSys/library/resources/configs/memspecs>.
- **Address Mapping**
There are currently two different file formats to describe the address mapping. This software automatically chooses the correct interpreter using the name of the xml root node as selection criterion.
Currently the CONGEN format is supported. It provides bit-wise granularity. It also provides the possibility of XOR address bits in order to map page misses to different banks and reduce latencies.
There is an optional field called **SOLUTION**. If added it will look for the solution with the field "ID" equals to 0.
Example with "SOLUTION" field at: <DRAMSys/library/resources/configs/amconfigs/congen_extended_solution.json>
Example without "SOLUTION" field at: <DRAMSys/library/resources/configs/amconfigs/congen_extended.json>
- **Standard XML file format**
XML files describe the address mapping to be used in the simulation.
Example for 1GB x64 DIMM with: 8 x 1 Gbit x8 Devices (Micron MT41J128M8) with Page Size: 1KB
[am_ddr3_8x1Gbx8_dimm_p1KB_brc.xml](DRAMSys/library/resources/configs/amconfigs/am_ddr3_8x1Gbx8_dimm_p1KB_brc.xml)
```xml
<!--
DDR3 Example:
1GB x64 DIMM with: 8 * 1 Gb x8 Devices (e.g. Micron MT41J128M8) with Page Size: 1KB
Device Characteristics:
Rows: 16 K [13:0] -> 14 bit
Bank: 8 [2:0] -> 3 bit
Cols: 1 K [9:0] -> 10 bit
Due to the DIMM we have a Byte Offset Y
2 2 2 | 2 2 2 2 2 2 2 1 1 1 1 1 1 1 | 1 1 1
9 8 7 | 6 5 4 3 2 1 0 9 8 7 6 5 4 3 | 2 1 0 9 8 7 6 5 4 3 | 2 1 0
B B B | R R R R R R R R R R R R R R | C C C C C C C C C C | Y Y Y
-->
<addressmapping>
<channel from="128" to="128" /> <!-- only one channel -->
<bank from="27" to="29" />
<row from="13" to="26" />
<column from="3" to="12" />
<bytes from="0" to="2" />
</addressmapping>
```
Some more examples with graphical representation follow:
[am_wideio.xml](DRAMSys/library/resources/configs/amconfigs/am_wideio.xml)
```xml
<!-- Row Bank Column -->
<addressmapping>
<channel from="27" to="28" />
<row from="14" to="26" />
<bank from="11" to="13" />
<column from="4" to="10" />
<bytes from="0" to="3" />
</addressmapping>
```
![Address Mapping Sample 1](DRAMSys/docs/images/am_wideio_rbc.png)
```xml
<!-- Bank Row Column -->
<addressmapping>
<channel from="27" to="28" />
<bank from="24" to="26" />
<row from="11" to="23" />
<column from="4" to="10" />
<bytes from="0" to="3" />
</addressmapping>
```
![Address Mapping Sample 2](DRAMSys/docs/images/am_wideio_brc.png)
- **ConGen XML file format**
@@ -483,44 +437,39 @@ Below, the sub-configurations are listed and explained.
Used data:
- "CONFIG": Gives you information about the ConGen configuration
- "SOLUTION":
- Attribute "ID": Unique identifier for this solution. It is used to specify a certain solution.
- "SOLUTION": (OBS.:Different solutions should be added as json objects inside the "SOLUTION" array)
- "ID": Unique identifier for this solution. It is used to specify a certain solution.
- "XOR": Defines an xor connection of a bank and row bit
- "BANK_BIT": Number of an address bit which is connected to a bank bit
- "ROW_BIT": Number of an address bit which is connected to a row bit
```xml
<CONGEN>
<NAME>test</NAME>
<COSTS>84</COSTS>
<CONFIG>
<NUM_BANK_BITS>3</NUM_BANK_BITS>
<NUM_ROW_BITS>14</NUM_ROW_BITS>
<NUM_COLUMN_BITS>10</NUM_COLUMN_BITS>
<NUM_BL_BITS>3</NUM_BL_BITS>
<NUM_BYTE_BITS>3</NUM_BYTE_BITS>
</CONFIG>
<SOLUTION ID="0">
<XOR BANK="29" ROW="16"/>
<BANK_BIT>28</BANK_BIT>
<BANK_BIT>27</BANK_BIT>
<BANK_BIT>29</BANK_BIT>
<ROW_BIT>16</ROW_BIT>
<ROW_BIT>11</ROW_BIT>
<ROW_BIT>14</ROW_BIT>
<ROW_BIT>15</ROW_BIT>
<ROW_BIT>25</ROW_BIT>
<ROW_BIT>26</ROW_BIT>
<ROW_BIT>22</ROW_BIT>
<ROW_BIT>24</ROW_BIT>
<ROW_BIT>23</ROW_BIT>
<ROW_BIT>21</ROW_BIT>
<ROW_BIT>20</ROW_BIT>
<ROW_BIT>19</ROW_BIT>
<ROW_BIT>18</ROW_BIT>
<ROW_BIT>17</ROW_BIT>
</SOLUTION>
</CONGEN>
```json
{
"CONGEN":
{"SOLUTION":[{
"XOR":[
{
"FIRST":13,
"SECOND":16
}
],
"BYTE_BIT": [
0,1,2
],
"COLUMN_BIT": [
3,4,5,6,7,8,9,10,11,12
],
"BANK_BIT": [
13,14,15
],
"ROW_BIT": [
16,17,18,19,20,21,22,23,24,25,26,27,28,29
],
"ID": 0
}]
}
}
```
@@ -528,57 +477,22 @@ Below, the sub-configurations are listed and explained.
An example follows.
```xml
<mcconfig>
<OpenPagePolicy value="1" />
<MaxNrOfTransactions value="8" />
<Scheduler value="Fifo" />
<Capsize value="5" />
<!-- 4 Modes: NoPowerDown, Staggered, TimeoutPDN, TimeoutSREF -->
<PowerDownMode value="NoPowerDown" />
<PowerDownTimeout value="100" />
<!-- Bankwise -->
<BankwiseLogic value="0"/>
<!-- Disable refresh. 0: no (refresh enabled), 1: yes (refresh disableb) -->
<ControllerCoreRefDisable value="0"/>
<!-- Refresh Mode. 1: 1X, 2: 2X, 4: 4X (e.g., DDR4) -->
<ControllerCoreRefMode value="1"/>
<!-- Number of AR commands in a tREFI in 1X mode -->
<ControllerCoreRefNumARCmdsIntREFI value="8192"/>
<!-- RGR -->
<ControllerCoreRGR value="0"/>
<ControllerCoreRGRRowInc value="1"/>
<!-- Banks to be refreshed in RGR mode. 1: yes, 0: no (max. 16 banks) -->
<ControllerCoreRGRB0 value="1"/>
<ControllerCoreRGRB1 value="1"/>
<ControllerCoreRGRB2 value="1"/>
<ControllerCoreRGRB3 value="1"/>
<ControllerCoreRGRB4 value="1"/>
<ControllerCoreRGRB5 value="1"/>
<ControllerCoreRGRB6 value="1"/>
<ControllerCoreRGRB7 value="1"/>
<ControllerCoreRGRB8 value="0"/>
<ControllerCoreRGRB9 value="0"/>
<ControllerCoreRGRB10 value="0"/>
<ControllerCoreRGRB11 value="0"/>
<ControllerCoreRGRB12 value="0"/>
<ControllerCoreRGRB13 value="0"/>
<ControllerCoreRGRB14 value="0"/>
<ControllerCoreRGRB15 value="0"/>
<!-- Timings for RGR normal or optimal values -->
<ControllerCoreRGRtRASBInClkCycles value="22"/>
<ControllerCoreRGRtRRDB_LInClkCycles value="2"/>
<ControllerCoreRGRtRRDB_SInClkCycles value="2"/>
<ControllerCoreRGRtRPBInClkCycles value="15"/>
<ControllerCoreRGRtRCBInClkCycles value="37"/>
<ControllerCoreRGRtFAWBInClkCycles value="0"/>
<!-- Postpone, pull-in -->
<ControllerCoreRefEnablePostpone value="0"/>
<ControllerCoreRefEnablePullIn value="0"/>
<ControllerCoreRefMaxPostponed value="8"/>
<ControllerCoreRefMaxPulledIn value="8"/>
<ControllerCoreRefForceMaxPostponeBurst value="0"/>
</mcconfig>
```json
{
"mcconfig": {
"PagePolicy": "Open",
"Scheduler": "Fifo",
"RequestBufferSize": "8",
"CmdMux": "Oldest",
"RespQueue": "Fifo",
"RefreshPolicy": "Rankwise",
"RefreshMode": "1",
"RefreshMaxPostponed": "8",
"RefreshMaxPulledin": "8",
"PowerDownPolicy": "NoPowerDown",
"PowerDownTimeout": "100"
}
}
```
- *BankwiseLogic* (boolean)
@@ -791,7 +705,7 @@ $ cd DRAMSys/library/resources
A description of the content each directory follows.
- **resources**
- **configs**: XML files that specify details of the simulation.
- **configs**: JSON files that specify details of the simulation.
- amconfigs: address mapping configs.
- mcconfigs: memory controller configs.
- memspecs: memory specification files (technology dependent).
@@ -867,9 +781,9 @@ There is a list of main configuration files on the top of the script:
```bash
sim_files="
ddr3-example.xml
ddr3-single-device.xml
wideio-example.xml
ddr3-example.json
ddr3-single-device.json
wideio-example.json
"
```
@@ -1205,53 +1119,6 @@ simulation server.
#### Usage Example with Thermal Simulation
The DRAMSys' main configuration file is presented below.
```xml
<simulation>
<!-- Configuration for the DRAMSys Simulator -->
<simconfig src="wideio_thermal.xml" />
<!-- Temperature Simulator Configuration -->
<thermalconfig src="confi.xml" />
<!-- Memory Device Specification: Which Device is on the DDR3 DIMM -->
<memspec src="WideIO.xml"></memspec>
<!-- Addressmapping Configuration of the Memory Controller -->
<addressmapping src="am_wideio.xml"></addressmapping>
<!-- Memory Controller Configuration: -->
<mcconfig src="fr_fcfs.xml"/>
<!--
The following trace setup is only used in standalone mode.
In library mode e.g. in Platform Architect the trace setup is ignored.
-->
<tracesetup>
<!--
This device mimics an image processing application
running on an FPGA with 200 Mhz.
-->
<device clkMhz="1000">test_error.stl</device>
</tracesetup>
</simulation>
```
Enable the error model in fr_fcfs.xml.
```xml
<memconfig>
<BankwiseLogic value="0"/>
<OpenPagePolicy value="1" />
<MaxNrOfTransactions value="8" />
<Scheduler value="FrFcfs" />
<Capsize value="5" />
<PowerDownMode value="NoPowerDown"/>
<PowerDownTimeout value="100" />
<!-- Error Model: -->
<ErrorChipSeed value="42" />
<ErrorCSVFile value="../../DRAMSys/library/src/error/error.csv" />
<!-- Modes: NoStorage, Store (store data without errormodel), ErrorModel (store data with errormodel) -->
<StoreMode value="ErrorModel" />
</memconfig>
```
Generate the input trace file for DRAMSys.
```bash
@@ -1382,7 +1249,7 @@ in a conf directory of this building directory.
Then the simulation can be started with:
```bash
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-example.xml config.ini 1
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-example.json config.ini 1
```
Let the simulation run for some seconds and then stop it with **CTRL-C**.
@@ -1396,7 +1263,7 @@ All essential files for some functional examples are provided.
Execute a hello world application:
```bash
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.xml ../../DRAMSys/gem5/configs/hello.ini 1
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/configs/hello.ini 1
```
A **Hello world!** message should be printed to the standard output.
@@ -1404,11 +1271,11 @@ A **Hello world!** message should be printed to the standard output.
Execute applications:
```bash
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.xml ../../DRAMSys/gem5/gem5_se/Oscar/config.ini 1
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/Oscar/config.ini 1
```
```bash
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.xml ../../DRAMSys/gem5/gem5_se/Bubblesort/config.ini 1
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/Bubblesort/config.ini 1
```
Wait some minutes for the application to finish.
@@ -1462,7 +1329,7 @@ library, benchmarks, disk image, etc.) can be obtained with [gem5.TnT].
Start a simulation. Example:
```bash
dram.sys/build/gem5$ ./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/rgrsim-gem5-fs.xml ../../DRAMSys/gem5/gem5_fs/parsec_arm_minor_2c_8GB/config.ini 1
dram.sys/build/gem5$ ./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/rgrsim-gem5-fs.json ../../DRAMSys/gem5/gem5_fs/parsec_arm_minor_2c_8GB/config.ini 1
```
Optionally, open another terminal or tab and connect to gem5.
@@ -1584,7 +1451,7 @@ executable=../../DRAMSys/gem5/gem5_se/parsec-arm/blackscholes/blackscholes
Start a simulation. Example:
```bash
dram.sys/build/gem5$ ./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/rgrsim-gem5-se.xml ../../DRAMSys/gem5/gem5_se/parsec-arm/config.ini 1
dram.sys/build/gem5$ ./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/rgrsim-gem5-se.json ../../DRAMSys/gem5/gem5_se/parsec-arm/config.ini 1
```
### Boot Linux with gem5 and DRAMSys
@@ -1607,42 +1474,35 @@ The config.ini should be copied again to the DRAMSys_gem5 build folder.
The simconfig should be changed in order to support storage and address offsets:
``` xml
<simconfig>
<SimulationName value="ddr3" />
<Debug value="0" />
<DatabaseRecording value="1" />
<PowerAnalysis value="1" />
<EnableWindowing value = "1" />
<WindowSize value="1000" />
<ThermalSimulation value="0"/>
<SimulationProgressBar value="1"/>
<NumberOfMemChannels value="1"/>
<NumberOfDevicesOnDIMM value = "8" />
<CheckTLM2Protocol value = "0" />
<ECCControllerMode value = "Disabled" />
<ErrorChipSeed value="42" />
<ErrorCSVFile value="" />
<!-- Modes:
- NoStorage,
- Store (store data without errormodel),
- ErrorModel (store data with errormodel)
-->
``` json
{
"simconfig": {
"CheckTLM2Protocol": "0",
"DatabaseRecording": "1",
"Debug": "0",
"ECCControllerMode": "Disabled",
"EnableWindowing": "0",
"ErrorCSVFile": "",
"ErrorChipSeed": "42",
"NumberOfDevicesOnDIMM": "8",
"NumberOfMemChannels": "1",
"PowerAnalysis": "0",
"SimulationName": "ddr3",
"SimulationProgressBar": "1",
"ThermalSimulation": "0",
"WindowSize": "1000"
<!-- Gem5 Related Configuration:
In the memory controller file the storage mode should be set to Store
E.g. the DRAM is located at 0x80000000 for gem5
-->
<StoreMode value="Store" />
<AddressOffset value = "2147483648" />
<UseMalloc value = "1" />
</simconfig>
"StoreMode": "Store",
"AddressOffset": "2147483648",
"UseMalloc": "1",
}
}
```
Then start DRAMSys_gem5 with the following command:
```bash
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-example.xml config.ini 1
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-example.json config.ini 1
```
For further sophisticated address mappings or scenarios checkout the file DRAMSys/gem5/main.cpp
@@ -1660,7 +1520,7 @@ tar -xaf DRAMSys/gem5/boot_linux/linux-aarch32-ael.img.tar.gz -C DRAMSys/gem5/bo
Execute the example:
```bash
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-boot-linux.xml ../../DRAMSys/gem5/configs/boot_linux.ini 1
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-boot-linux.json ../../DRAMSys/gem5/configs/boot_linux.ini 1
```
Open a new terminal and connect to gem5:
@@ -1683,7 +1543,7 @@ python files are stored [here](DRAMSys/gem5/examples).
This is an example for running an elastic trace:
```bash
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-example.xml ../../DRAMSys/gem5/configs/singleElasticTraceReplay.ini 1
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-example.json ../../DRAMSys/gem5/configs/singleElasticTraceReplay.ini 1
```
An overview of the architcture being simulated is presented below:
@@ -1695,13 +1555,13 @@ Note that the address offset is usually zero for elastic traces.
Another example with L2 cache:
```bash
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-example.xml ../../DRAMSys/gem5/configs/singleElasticTraceReplayWithL2.ini 1
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-example.json ../../DRAMSys/gem5/configs/singleElasticTraceReplayWithL2.ini 1
```
If two elastic traces should be used run the simulation with the following example:
```
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-example.xml ../../DRAMSys/gem5/configs/dualElasticTraceReplay.ini 2
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-example.json ../../DRAMSys/gem5/configs/dualElasticTraceReplay.ini 2
```
An overview of the architcture being simulated is presented below:
@@ -1916,7 +1776,7 @@ After building, go the the folder where *DRAMSys_gem5* is located.
Test with a hello world application for X86.
```bash
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.xml ../../DRAMSys/gem5/gem5_se/hello-x86/config.ini 1
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/hello-x86/config.ini 1
```
A **Hello world!** message should be printed to the standard output.
@@ -1931,98 +1791,98 @@ Examples:
**Basicmath**
```bash
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.xml ../../DRAMSys/gem5/gem5_se/MiBench/automotive/basicmath/small/config.ini 1
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.xml ../../DRAMSys/gem5/gem5_se/MiBench/automotive/basicmath/large/config.ini 1
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/automotive/basicmath/small/config.ini 1
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/automotive/basicmath/large/config.ini 1
```
**Bitcount**
```bash
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.xml ../../DRAMSys/gem5/gem5_se/MiBench/automotive/bitcount/small/config.ini 1
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.xml ../../DRAMSys/gem5/gem5_se/MiBench/automotive/bitcount/large/config.ini 1
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/automotive/bitcount/small/config.ini 1
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/automotive/bitcount/large/config.ini 1
```
**Qsort**
```bash
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.xml ../../DRAMSys/gem5/gem5_se/MiBench/automotive/qsort/small/config.ini 1
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.xml ../../DRAMSys/gem5/gem5_se/MiBench/automotive/qsort/large/config.ini 1
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/automotive/qsort/small/config.ini 1
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/automotive/qsort/large/config.ini 1
```
**Susan**
```bash
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.xml ../../DRAMSys/gem5/gem5_se/MiBench/automotive/susan/small/corners/config.ini 1
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.xml ../../DRAMSys/gem5/gem5_se/MiBench/automotive/susan/large/corners/config.ini 1
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/automotive/susan/small/corners/config.ini 1
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/automotive/susan/large/corners/config.ini 1
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.xml ../../DRAMSys/gem5/gem5_se/MiBench/automotive/susan/small/edges/config.ini 1
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.xml ../../DRAMSys/gem5/gem5_se/MiBench/automotive/susan/large/edges/config.ini 1
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/automotive/susan/small/edges/config.ini 1
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/automotive/susan/large/edges/config.ini 1
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.xml ../../DRAMSys/gem5/gem5_se/MiBench/automotive/susan/small/smoothing/config.ini 1
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.xml ../../DRAMSys/gem5/gem5_se/MiBench/automotive/susan/large/smoothing/config.ini 1
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/automotive/susan/small/smoothing/config.ini 1
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/automotive/susan/large/smoothing/config.ini 1
```
**Network Applications**
**Dijkstra**
```bash
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.xml ../../DRAMSys/gem5/gem5_se/MiBench/network/dijkstra/small/config.ini 1
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.xml ../../DRAMSys/gem5/gem5_se/MiBench/network/dijkstra/large/config.ini 1
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/network/dijkstra/small/config.ini 1
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/network/dijkstra/large/config.ini 1
```
**Patricia**
```bash
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.xml ../../DRAMSys/gem5/gem5_se/MiBench/network/patricia/small/config.ini 1
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.xml ../../DRAMSys/gem5/gem5_se/MiBench/network/patricia/large/config.ini 1
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/network/patricia/small/config.ini 1
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/network/patricia/large/config.ini 1
```
**Security Applications**
**Blowfish Encode**
```bash
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.xml ../../DRAMSys/gem5/gem5_se/MiBench/security/blowfish/encode/small/config.ini 1
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.xml ../../DRAMSys/gem5/gem5_se/MiBench/security/blowfish/encode/large/config.ini 1
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/security/blowfish/encode/small/config.ini 1
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/security/blowfish/encode/large/config.ini 1
```
**Blowfish Decode**
```bash
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.xml ../../DRAMSys/gem5/gem5_se/MiBench/security/blowfish/decode/small/config.ini 1
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.xml ../../DRAMSys/gem5/gem5_se/MiBench/security/blowfish/decode/large/config.ini 1
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/security/blowfish/decode/small/config.ini 1
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/security/blowfish/decode/large/config.ini 1
```
**SHA**
```bash
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.xml ../../DRAMSys/gem5/gem5_se/MiBench/security/sha/small/config.ini 1
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.xml ../../DRAMSys/gem5/gem5_se/MiBench/security/sha/large/config.ini 1
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/security/sha/small/config.ini 1
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/security/sha/large/config.ini 1
```
**Telecom Applications**
**CRC32**
```bash
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.xml ../../DRAMSys/gem5/gem5_se/MiBench/telecomm/crc32/small/config.ini 1
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.xml ../../DRAMSys/gem5/gem5_se/MiBench/telecomm/crc32/large/config.ini 1
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/telecomm/crc32/small/config.ini 1
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/telecomm/crc32/large/config.ini 1
```
**FFT**
```bash
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.xml ../../DRAMSys/gem5/gem5_se/MiBench/telecomm/fft/small/config.ini 1
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.xml ../../DRAMSys/gem5/gem5_se/MiBench/telecomm/fft/large/config.ini 1
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/telecomm/fft/small/config.ini 1
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/telecomm/fft/large/config.ini 1
```
**FFT-INV**
```bash
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.xml ../../DRAMSys/gem5/gem5_se/MiBench/telecomm/fft-inv/small/config.ini 1
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.xml ../../DRAMSys/gem5/gem5_se/MiBench/telecomm/fft-inv/large/config.ini 1
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/telecomm/fft-inv/small/config.ini 1
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/telecomm/fft-inv/large/config.ini 1
```
**GSM Encode**
```bash
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.xml ../../DRAMSys/gem5/gem5_se/MiBench/telecomm/gsm/encode/small/config.ini 1
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.xml ../../DRAMSys/gem5/gem5_se/MiBench/telecomm/gsm/encode/large/config.ini 1
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/telecomm/gsm/encode/small/config.ini 1
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/telecomm/gsm/encode/large/config.ini 1
```
**GSM Decode**
```bash
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.xml ../../DRAMSys/gem5/gem5_se/MiBench/telecomm/gsm/decode/small/config.ini 1
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.xml ../../DRAMSys/gem5/gem5_se/MiBench/telecomm/gsm/decode/large/config.ini 1
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/telecomm/gsm/decode/small/config.ini 1
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/telecomm/gsm/decode/large/config.ini 1
```
Check the folder [DRAMSys/gem5/gem5_se/MiBench](DRAMSys/gem5/gem5_se/MiBench) for all applications and configuration files.
@@ -2041,7 +1901,7 @@ library, benchmarks, disk image, etc.) can be obtained with [gem5.TnT].
Start a simulation. Example:
```bash
dram.sys/build/gem5$ ./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/rgrsim-gem5-fs.xml ../../DRAMSys/gem5/gem5_fs/arm64/config.ini 1
dram.sys/build/gem5$ ./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/rgrsim-gem5-fs.json ../../DRAMSys/gem5/gem5_fs/arm64/config.ini 1
```
Optionally, open another terminal or tab and connect to gem5.