From efdfd7fc3dc2224266dadd4d569260cd9b4c1c80 Mon Sep 17 00:00:00 2001 From: scorrea Date: Wed, 20 May 2020 11:13:48 +0200 Subject: [PATCH] numbers and bools written without string quotes --- .../resources/configs/mcconfigs/fifo.json | 10 +- .../configs/mcconfigs/fifoStrict.json | 10 +- .../resources/configs/mcconfigs/fr_fcfs.json | 12 +- .../configs/mcconfigs/fr_fcfs_grp.json | 13 +- .../configs/simulator/ddr3-single-device.json | 26 +-- .../resources/configs/simulator/ddr3.json | 26 +-- .../configs/simulator/ddr3_boot_linux.json | 26 +-- .../resources/configs/simulator/ddr3_ecc.json | 26 +-- .../configs/simulator/ddr3_gem5_se.json | 26 +-- .../resources/configs/simulator/ddr4.json | 26 +-- .../resources/configs/simulator/hbm2.json | 26 +-- .../resources/configs/simulator/lpddr4.json | 26 +-- .../resources/configs/simulator/orgr.json | 70 +++--- .../simulator/orgr_4b_opt_timings_ddr3.json | 72 +++---- .../simulator/orgr_4b_std_timings_ddr3.json | 74 ++++--- .../simulator/orgr_8b_opt_timings_ddr3.json | 72 +++---- .../simulator/orgr_8b_std_timings_ddr3.json | 74 ++++--- .../configs/simulator/orgr_ddr4.json | 26 +-- .../configs/simulator/rgrsimcfg-gem5-fs.json | 26 +-- .../configs/simulator/rgrsimcfg-gem5-se.json | 26 +-- .../configs/simulator/rgrsimcfg.json | 26 +-- .../resources/configs/simulator/sms.json | 22 +- .../resources/configs/simulator/wideio.json | 24 +-- .../configs/simulator/wideio_ecc.json | 24 +-- .../configs/simulator/wideio_thermal.json | 24 +-- .../resources/configs/thermalsim/config.json | 14 +- .../configs/thermalsim/powerInfo.json | 16 +- .../resources/simulations/ddr3-ecc.json | 4 +- .../resources/simulations/ddr3-example.json | 4 +- .../resources/simulations/ddr3-example2.json | 6 +- .../simulations/ddr3-single-device.json | 4 +- .../simulations/ddr3_postpone_ref_test.json | 4 +- .../resources/simulations/ddr4-example.json | 4 +- .../resources/simulations/hbm2-example.json | 4 +- .../resources/simulations/lpddr4-example.json | 4 +- .../resources/simulations/ranktest.json | 4 +- .../library/resources/simulations/rgrsim.json | 4 +- .../resources/simulations/sms-example.json | 8 +- .../resources/simulations/wideio-ecc.json | 4 +- .../resources/simulations/wideio-example.json | 4 +- .../src/configuration/Configuration.cpp | 52 ++--- .../library/src/configuration/Configuration.h | 2 +- .../src/configuration/TemperatureSimConfig.h | 7 +- README.md | 203 +++++++++--------- 44 files changed, 589 insertions(+), 576 deletions(-) diff --git a/DRAMSys/library/resources/configs/mcconfigs/fifo.json b/DRAMSys/library/resources/configs/mcconfigs/fifo.json index 0da9e947..97c33e69 100644 --- a/DRAMSys/library/resources/configs/mcconfigs/fifo.json +++ b/DRAMSys/library/resources/configs/mcconfigs/fifo.json @@ -1,11 +1,11 @@ {"mcconfig": {"PagePolicy": "Open", "Scheduler": "Fifo", -"RequestBufferSize": "8", +"RequestBufferSize": 8, "CmdMux": "Oldest", "RespQueue": "Fifo", "RefreshPolicy": "Rankwise", -"RefreshMode": "1", -"RefreshMaxPostponed": "8", -"RefreshMaxPulledin": "8", +"RefreshMode": 1, +"RefreshMaxPostponed": 8, +"RefreshMaxPulledin": 8, "PowerDownPolicy": "NoPowerDown", -"PowerDownTimeout": "100"}} +"PowerDownTimeout": 100}} diff --git a/DRAMSys/library/resources/configs/mcconfigs/fifoStrict.json b/DRAMSys/library/resources/configs/mcconfigs/fifoStrict.json index 95cd1871..3bce6c6e 100644 --- a/DRAMSys/library/resources/configs/mcconfigs/fifoStrict.json +++ b/DRAMSys/library/resources/configs/mcconfigs/fifoStrict.json @@ -1,11 +1,11 @@ {"mcconfig": {"PagePolicy": "Open", "Scheduler": "Fifo", -"RequestBufferSize": "8", +"RequestBufferSize": 8, "CmdMux": "Strict", "RespQueue": "Fifo", "RefreshPolicy": "Rankwise", -"RefreshMode": "1", -"RefreshMaxPostponed": "8", -"RefreshMaxPulledin": "8", +"RefreshMode": 1, +"RefreshMaxPostponed": 8, +"RefreshMaxPulledin": 8, "PowerDownPolicy": "NoPowerDown", -"PowerDownTimeout": "100"}} \ No newline at end of file +"PowerDownTimeout": 100}} diff --git a/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs.json b/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs.json index 722147a1..5eea8b88 100644 --- a/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs.json +++ b/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs.json @@ -1,2 +1,12 @@ {"mcconfig": { -"PagePolicy": "Open", "Scheduler": "FrFcfs", "RequestBufferSize": "8", "CmdMux": "Oldest", "RespQueue": "Fifo", "RefreshPolicy": "Rankwise", "RefreshMode": "1", "RefreshMaxPostponed": "8", "RefreshMaxPulledin": "8", "PowerDownPolicy": "NoPowerDown", "PowerDownTimeout": "100"}} + "PagePolicy": "Open", + "Scheduler": "FrFcfs", + "RequestBufferSize": 8, + "CmdMux": "Oldest", + "RespQueue": "Fifo", + "RefreshPolicy": "Rankwise", + "RefreshMode": 1, + "RefreshMaxPostponed": 8, + "RefreshMaxPulledin": 8, + "PowerDownPolicy": "NoPowerDown", + "PowerDownTimeout": 100}} diff --git a/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_grp.json b/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_grp.json index 9cff3e26..b6364345 100644 --- a/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_grp.json +++ b/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_grp.json @@ -1 +1,12 @@ -{"mcconfig": {"PagePolicy": "Open", "Scheduler": "FrFcfsGrp", "RequestBufferSize": "8", "CmdMux": "Oldest", "RespQueue": "Fifo", "RefreshPolicy": "Rankwise", "RefreshMode": "1", "RefreshMaxPostponed": "8", "RefreshMaxPulledin": "8", "PowerDownPolicy": "NoPowerDown", "PowerDownTimeout": "100"}} +{"mcconfig": + {"PagePolicy": "Open", + "Scheduler": "FrFcfsGrp", + "RequestBufferSize": 8, + "CmdMux": "Oldest", + "RespQueue": "Fifo", + "RefreshPolicy": "Rankwise", + "RefreshMode": 1, + "RefreshMaxPostponed": 8, + "RefreshMaxPulledin": 8, + "PowerDownPolicy": "NoPowerDown", + "PowerDownTimeout": 100}} diff --git a/DRAMSys/library/resources/configs/simulator/ddr3-single-device.json b/DRAMSys/library/resources/configs/simulator/ddr3-single-device.json index 8071a126..a1621422 100644 --- a/DRAMSys/library/resources/configs/simulator/ddr3-single-device.json +++ b/DRAMSys/library/resources/configs/simulator/ddr3-single-device.json @@ -1,21 +1,21 @@ { "simconfig": { - "AddressOffset": "0", - "CheckTLM2Protocol": "0", - "DatabaseRecording": "1", - "Debug": "0", + "AddressOffset": 0, + "CheckTLM2Protocol": false, + "DatabaseRecording": true, + "Debug": false, "ECCControllerMode": "Disabled", - "EnableWindowing": "1", + "EnableWindowing": true, "ErrorCSVFile": "", - "ErrorChipSeed": "42", - "NumberOfDevicesOnDIMM": "1", - "NumberOfMemChannels": "1", - "PowerAnalysis": "1", + "ErrorChipSeed": 42, + "NumberOfDevicesOnDIMM": 1, + "NumberOfMemChannels": 1, + "PowerAnalysis": true, "SimulationName": "ddr3_single_dev", - "SimulationProgressBar": "1", + "SimulationProgressBar": true, "StoreMode": "NoStorage", - "ThermalSimulation": "0", - "UseMalloc": "0", - "WindowSize": "1000" + "ThermalSimulation": false, + "UseMalloc": false, + "WindowSize": 1000 } } \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/simulator/ddr3.json b/DRAMSys/library/resources/configs/simulator/ddr3.json index 91722b4e..4c08d8a0 100644 --- a/DRAMSys/library/resources/configs/simulator/ddr3.json +++ b/DRAMSys/library/resources/configs/simulator/ddr3.json @@ -1,21 +1,21 @@ { "simconfig": { - "AddressOffset": "0", - "CheckTLM2Protocol": "0", - "DatabaseRecording": "1", - "Debug": "0", + "AddressOffset": 0, + "CheckTLM2Protocol": false, + "DatabaseRecording": true, + "Debug": false, "ECCControllerMode": "Disabled", - "EnableWindowing": "0", + "EnableWindowing": false, "ErrorCSVFile": "", - "ErrorChipSeed": "42", - "NumberOfDevicesOnDIMM": "8", - "NumberOfMemChannels": "1", - "PowerAnalysis": "0", + "ErrorChipSeed": 42, + "NumberOfDevicesOnDIMM": 8, + "NumberOfMemChannels": 1, + "PowerAnalysis": false, "SimulationName": "ddr3", - "SimulationProgressBar": "1", + "SimulationProgressBar": true, "StoreMode": "NoStorage", - "ThermalSimulation": "0", - "UseMalloc": "0", - "WindowSize": "1000" + "ThermalSimulation": false, + "UseMalloc": false, + "WindowSize": 1000 } } \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/simulator/ddr3_boot_linux.json b/DRAMSys/library/resources/configs/simulator/ddr3_boot_linux.json index ff8d2771..fd35bdee 100644 --- a/DRAMSys/library/resources/configs/simulator/ddr3_boot_linux.json +++ b/DRAMSys/library/resources/configs/simulator/ddr3_boot_linux.json @@ -1,21 +1,21 @@ { "simconfig": { - "AddressOffset": "2147483648", - "CheckTLM2Protocol": "0", - "DatabaseRecording": "1", - "Debug": "0", + "AddressOffset": 2147483648, + "CheckTLM2Protocol": false, + "DatabaseRecording": true, + "Debug": false, "ECCControllerMode": "Disabled", - "EnableWindowing": "1", + "EnableWindowing": true, "ErrorCSVFile": "", - "ErrorChipSeed": "42", - "NumberOfDevicesOnDIMM": "8", - "NumberOfMemChannels": "1", - "PowerAnalysis": "1", + "ErrorChipSeed": 42, + "NumberOfDevicesOnDIMM": 8, + "NumberOfMemChannels": 1, + "PowerAnalysis": true, "SimulationName": "ddr3", - "SimulationProgressBar": "1", + "SimulationProgressBar": true, "StoreMode": "Store", - "ThermalSimulation": "0", - "UseMalloc": "1", - "WindowSize": "1000" + "ThermalSimulation": false, + "UseMalloc": true, + "WindowSize": 1000 } } \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/simulator/ddr3_ecc.json b/DRAMSys/library/resources/configs/simulator/ddr3_ecc.json index d122fe30..2b813f99 100644 --- a/DRAMSys/library/resources/configs/simulator/ddr3_ecc.json +++ b/DRAMSys/library/resources/configs/simulator/ddr3_ecc.json @@ -1,21 +1,21 @@ { "simconfig": { - "AddressOffset": "0", - "CheckTLM2Protocol": "0", - "DatabaseRecording": "1", - "Debug": "0", + "AddressOffset": 0, + "CheckTLM2Protocol": false, + "DatabaseRecording": true, + "Debug": false, "ECCControllerMode": "Hamming", - "EnableWindowing": "1", + "EnableWindowing": true, "ErrorCSVFile": "", - "ErrorChipSeed": "42", - "NumberOfDevicesOnDIMM": "8", - "NumberOfMemChannels": "1", - "PowerAnalysis": "1", + "ErrorChipSeed": 42, + "NumberOfDevicesOnDIMM": 8, + "NumberOfMemChannels": 1, + "PowerAnalysis": true, "SimulationName": "ddr3", - "SimulationProgressBar": "1", + "SimulationProgressBar": true, "StoreMode": "ErrorModel", - "ThermalSimulation": "0", - "UseMalloc": "0", - "WindowSize": "1000" + "ThermalSimulation": false, + "UseMalloc": false, + "WindowSize": 1000 } } \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/simulator/ddr3_gem5_se.json b/DRAMSys/library/resources/configs/simulator/ddr3_gem5_se.json index 40fa64f0..72ebcf9b 100644 --- a/DRAMSys/library/resources/configs/simulator/ddr3_gem5_se.json +++ b/DRAMSys/library/resources/configs/simulator/ddr3_gem5_se.json @@ -1,21 +1,21 @@ { "simconfig": { - "AddressOffset": "0", - "CheckTLM2Protocol": "0", - "DatabaseRecording": "1", - "Debug": "0", + "AddressOffset": 0, + "CheckTLM2Protocol": false, + "DatabaseRecording": true, + "Debug": false, "ECCControllerMode": "Disabled", - "EnableWindowing": "1", + "EnableWindowing": true, "ErrorCSVFile": "", - "ErrorChipSeed": "42", - "NumberOfDevicesOnDIMM": "8", - "NumberOfMemChannels": "1", - "PowerAnalysis": "1", + "ErrorChipSeed": 42, + "NumberOfDevicesOnDIMM": 8, + "NumberOfMemChannels": 1, + "PowerAnalysis": true, "SimulationName": "ddr3", - "SimulationProgressBar": "1", + "SimulationProgressBar": true, "StoreMode": "Store", - "ThermalSimulation": "0", - "UseMalloc": "0", - "WindowSize": "1000" + "ThermalSimulation": false, + "UseMalloc": false, + "WindowSize": 1000 } } \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/simulator/ddr4.json b/DRAMSys/library/resources/configs/simulator/ddr4.json index 3566136f..8e62e680 100644 --- a/DRAMSys/library/resources/configs/simulator/ddr4.json +++ b/DRAMSys/library/resources/configs/simulator/ddr4.json @@ -1,21 +1,21 @@ { "simconfig": { - "AddressOffset": "0", - "CheckTLM2Protocol": "0", - "DatabaseRecording": "1", - "Debug": "0", + "AddressOffset": 0, + "CheckTLM2Protocol": false, + "DatabaseRecording": true, + "Debug": false, "ECCControllerMode": "Disabled", - "EnableWindowing": "0", + "EnableWindowing": false, "ErrorCSVFile": "", - "ErrorChipSeed": "42", - "NumberOfDevicesOnDIMM": "8", - "NumberOfMemChannels": "1", - "PowerAnalysis": "0", + "ErrorChipSeed": 42, + "NumberOfDevicesOnDIMM": 8, + "NumberOfMemChannels": 1, + "PowerAnalysis": false, "SimulationName": "ddr4", - "SimulationProgressBar": "1", + "SimulationProgressBar": true, "StoreMode": "NoStorage", - "ThermalSimulation": "0", - "UseMalloc": "0", - "WindowSize": "1000" + "ThermalSimulation": false, + "UseMalloc": false, + "WindowSize": 1000 } } \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/simulator/hbm2.json b/DRAMSys/library/resources/configs/simulator/hbm2.json index 102fe545..9589611f 100644 --- a/DRAMSys/library/resources/configs/simulator/hbm2.json +++ b/DRAMSys/library/resources/configs/simulator/hbm2.json @@ -1,21 +1,21 @@ { "simconfig": { - "AddressOffset": "0", - "CheckTLM2Protocol": "0", - "DatabaseRecording": "1", - "Debug": "0", + "AddressOffset": 0, + "CheckTLM2Protocol": false, + "DatabaseRecording": true, + "Debug": false, "ECCControllerMode": "Disabled", - "EnableWindowing": "0", + "EnableWindowing": false, "ErrorCSVFile": "", - "ErrorChipSeed": "42", - "NumberOfDevicesOnDIMM": "1", - "NumberOfMemChannels": "1", - "PowerAnalysis": "0", + "ErrorChipSeed": 42, + "NumberOfDevicesOnDIMM": 1, + "NumberOfMemChannels": 1, + "PowerAnalysis": false, "SimulationName": "hbm2", - "SimulationProgressBar": "1", + "SimulationProgressBar": true, "StoreMode": "NoStorage", - "ThermalSimulation": "0", - "UseMalloc": "0", - "WindowSize": "1000" + "ThermalSimulation": false, + "UseMalloc": false, + "WindowSize": 1000 } } \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/simulator/lpddr4.json b/DRAMSys/library/resources/configs/simulator/lpddr4.json index 760ddbcb..fd8fe855 100644 --- a/DRAMSys/library/resources/configs/simulator/lpddr4.json +++ b/DRAMSys/library/resources/configs/simulator/lpddr4.json @@ -1,21 +1,21 @@ { "simconfig": { - "AddressOffset": "0", - "CheckTLM2Protocol": "0", - "DatabaseRecording": "1", - "Debug": "0", + "AddressOffset": 0, + "CheckTLM2Protocol": false, + "DatabaseRecording": true, + "Debug": false, "ECCControllerMode": "Disabled", - "EnableWindowing": "0", + "EnableWindowing": false, "ErrorCSVFile": "", - "ErrorChipSeed": "42", - "NumberOfDevicesOnDIMM": "1", - "NumberOfMemChannels": "1", - "PowerAnalysis": "0", + "ErrorChipSeed": 42, + "NumberOfDevicesOnDIMM": 1, + "NumberOfMemChannels": 1, + "PowerAnalysis": false, "SimulationName": "lpddr4", - "SimulationProgressBar": "1", + "SimulationProgressBar": true, "StoreMode": "NoStorage", - "ThermalSimulation": "0", - "UseMalloc": "0", - "WindowSize": "1000" + "ThermalSimulation": false, + "UseMalloc": false, + "WindowSize": 1000 } } \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/simulator/orgr.json b/DRAMSys/library/resources/configs/simulator/orgr.json index a9445926..f4972a80 100644 --- a/DRAMSys/library/resources/configs/simulator/orgr.json +++ b/DRAMSys/library/resources/configs/simulator/orgr.json @@ -1,40 +1,40 @@ { "simconfig": { - "ControllerCoreRGR": "1", - "ControllerCoreRGRB0": "1", - "ControllerCoreRGRB1": "1", - "ControllerCoreRGRB10": "0", - "ControllerCoreRGRB11": "0", - "ControllerCoreRGRB12": "0", - "ControllerCoreRGRB13": "0", - "ControllerCoreRGRB14": "0", - "ControllerCoreRGRB15": "0", - "ControllerCoreRGRB2": "1", - "ControllerCoreRGRB3": "1", - "ControllerCoreRGRB4": "1", - "ControllerCoreRGRB5": "1", - "ControllerCoreRGRB6": "1", - "ControllerCoreRGRB7": "1", - "ControllerCoreRGRB8": "0", - "ControllerCoreRGRB9": "0", - "ControllerCoreRGRtFAWBInClkCycles": "27", - "ControllerCoreRGRtRASBInClkCycles": "20", - "ControllerCoreRGRtRCBInClkCycles": "27", - "ControllerCoreRGRtRPBInClkCycles": "8", - "ControllerCoreRGRtRRDB_LInClkCycles": "6", - "ControllerCoreRGRtRRDB_SInClkCycles": "6", - "ControllerCoreRefDisable": "0", - "ControllerCoreRefNumARCmdsIntREFI": "8192", - "DatabaseRecording": "1", - "Debug": "0", - "EnableWindowing": "1", - "NumberOfDevicesOnDIMM": "4", - "NumberOfMemChannels": "1", - "PowerAnalysis": "1", + "ControllerCoreRGR": true, + "ControllerCoreRGRB0": true, + "ControllerCoreRGRB1": true, + "ControllerCoreRGRB10": false, + "ControllerCoreRGRB11": false, + "ControllerCoreRGRB12": false, + "ControllerCoreRGRB13": false, + "ControllerCoreRGRB14": false, + "ControllerCoreRGRB15": false, + "ControllerCoreRGRB2": true, + "ControllerCoreRGRB3": true, + "ControllerCoreRGRB4": true, + "ControllerCoreRGRB5": true, + "ControllerCoreRGRB6": true, + "ControllerCoreRGRB7": true, + "ControllerCoreRGRB8": false, + "ControllerCoreRGRB9": false, + "ControllerCoreRGRtFAWBInClkCycles": 27, + "ControllerCoreRGRtRASBInClkCycles": 20, + "ControllerCoreRGRtRCBInClkCycles": 27, + "ControllerCoreRGRtRPBInClkCycles": 8, + "ControllerCoreRGRtRRDB_LInClkCycles": 6, + "ControllerCoreRGRtRRDB_SInClkCycles": 6, + "ControllerCoreRefDisable": 0, + "ControllerCoreRefNumARCmdsIntREFI": 8192, + "DatabaseRecording": true, + "Debug": false, + "EnableWindowing": true, + "NumberOfDevicesOnDIMM": 4, + "NumberOfMemChannels": 1, + "PowerAnalysis": true, "SimulationName": "orgr", - "SimulationProgressBar": "1", - "ThermalSimulation": "0", - "UseMalloc": "0", - "WindowSize": "1000" + "SimulationProgressBar": true, + "ThermalSimulation": false, + "UseMalloc": false, + "WindowSize": 1000 } } diff --git a/DRAMSys/library/resources/configs/simulator/orgr_4b_opt_timings_ddr3.json b/DRAMSys/library/resources/configs/simulator/orgr_4b_opt_timings_ddr3.json index 180cfdf2..a39065dc 100644 --- a/DRAMSys/library/resources/configs/simulator/orgr_4b_opt_timings_ddr3.json +++ b/DRAMSys/library/resources/configs/simulator/orgr_4b_opt_timings_ddr3.json @@ -1,40 +1,40 @@ { "simconfig": { - "ControllerCoreRGR": "1", - "ControllerCoreRGRB0": "1", - "ControllerCoreRGRB1": "1", - "ControllerCoreRGRB10": "0", - "ControllerCoreRGRB11": "0", - "ControllerCoreRGRB12": "0", - "ControllerCoreRGRB13": "0", - "ControllerCoreRGRB14": "0", - "ControllerCoreRGRB15": "0", - "ControllerCoreRGRB2": "1", - "ControllerCoreRGRB3": "1", - "ControllerCoreRGRB4": "0", - "ControllerCoreRGRB5": "0", - "ControllerCoreRGRB6": "0", - "ControllerCoreRGRB7": "0", - "ControllerCoreRGRB8": "0", - "ControllerCoreRGRB9": "0", - "ControllerCoreRGRtFAWBInClkCycles": "0", - "ControllerCoreRGRtRASBInClkCycles": "11", - "ControllerCoreRGRtRCBInClkCycles": "16", - "ControllerCoreRGRtRPBInClkCycles": "5", - "ControllerCoreRGRtRRDB_LInClkCycles": "2", - "ControllerCoreRGRtRRDB_SInClkCycles": "2", - "ControllerCoreRefDisable": "0", - "ControllerCoreRefNumARCmdsIntREFI": "8192", - "DatabaseRecording": "1", - "Debug": "0", - "EnableWindowing": "1", - "NumberOfDevicesOnDIMM": "4", - "NumberOfMemChannels": "1", - "PowerAnalysis": "1", + "ControllerCoreRGR": true, + "ControllerCoreRGRB0": true, + "ControllerCoreRGRB1": true, + "ControllerCoreRGRB10": false, + "ControllerCoreRGRB11": false, + "ControllerCoreRGRB12": false, + "ControllerCoreRGRB13": false, + "ControllerCoreRGRB14": false, + "ControllerCoreRGRB15": false, + "ControllerCoreRGRB2": true, + "ControllerCoreRGRB3": true, + "ControllerCoreRGRB4": false, + "ControllerCoreRGRB5": false, + "ControllerCoreRGRB6": false, + "ControllerCoreRGRB7": false, + "ControllerCoreRGRB8": false, + "ControllerCoreRGRB9": false, + "ControllerCoreRGRtFAWBInClkCycles": 0, + "ControllerCoreRGRtRASBInClkCycles": 11, + "ControllerCoreRGRtRCBInClkCycles": 16, + "ControllerCoreRGRtRPBInClkCycles": 5, + "ControllerCoreRGRtRRDB_LInClkCycles": 2, + "ControllerCoreRGRtRRDB_SInClkCycles": 2, + "ControllerCoreRefDisable": 0, + "ControllerCoreRefNumARCmdsIntREFI": 8192, + "DatabaseRecording": true, + "Debug": false, + "EnableWindowing": true, + "NumberOfDevicesOnDIMM": 4, + "NumberOfMemChannels": 1, + "PowerAnalysis": true, "SimulationName": "orgr_4b_opt_timings", - "SimulationProgressBar": "1", - "ThermalSimulation": "0", - "UseMalloc": "0", - "WindowSize": "1000" + "SimulationProgressBar": true, + "ThermalSimulation": false, + "UseMalloc": false, + "WindowSize": 1000 } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/simulator/orgr_4b_std_timings_ddr3.json b/DRAMSys/library/resources/configs/simulator/orgr_4b_std_timings_ddr3.json index a532307c..4903b8d5 100644 --- a/DRAMSys/library/resources/configs/simulator/orgr_4b_std_timings_ddr3.json +++ b/DRAMSys/library/resources/configs/simulator/orgr_4b_std_timings_ddr3.json @@ -1,42 +1,40 @@ { "simconfig": { - "ControllerCoreRGR": { - "@value": "1" - }, - "ControllerCoreRGRB0": "1", - "ControllerCoreRGRB1": "1", - "ControllerCoreRGRB10": "0", - "ControllerCoreRGRB11": "0", - "ControllerCoreRGRB12": "0", - "ControllerCoreRGRB13": "0", - "ControllerCoreRGRB14": "0", - "ControllerCoreRGRB15": "0", - "ControllerCoreRGRB2": "1", - "ControllerCoreRGRB3": "1", - "ControllerCoreRGRB4": "0", - "ControllerCoreRGRB5": "0", - "ControllerCoreRGRB6": "0", - "ControllerCoreRGRB7": "0", - "ControllerCoreRGRB8": "0", - "ControllerCoreRGRB9": "0", - "ControllerCoreRGRtFAWBInClkCycles": "27", - "ControllerCoreRGRtRASBInClkCycles": "20", - "ControllerCoreRGRtRCBInClkCycles": "27", - "ControllerCoreRGRtRPBInClkCycles": "8", - "ControllerCoreRGRtRRDB_LInClkCycles": "6", - "ControllerCoreRGRtRRDB_SInClkCycles": "6", - "ControllerCoreRefDisable": "0", - "ControllerCoreRefNumARCmdsIntREFI": "8192", - "DatabaseRecording": "1", - "Debug": "0", - "EnableWindowing": "1", - "NumberOfDevicesOnDIMM": "4", - "NumberOfMemChannels": "1", - "PowerAnalysis": "1", + "ControllerCoreRGR": true, + "ControllerCoreRGRB0": true, + "ControllerCoreRGRB1": true, + "ControllerCoreRGRB10": false, + "ControllerCoreRGRB11": false, + "ControllerCoreRGRB12": false, + "ControllerCoreRGRB13": false, + "ControllerCoreRGRB14": false, + "ControllerCoreRGRB15": false, + "ControllerCoreRGRB2": true, + "ControllerCoreRGRB3": true, + "ControllerCoreRGRB4": false, + "ControllerCoreRGRB5": false, + "ControllerCoreRGRB6": false, + "ControllerCoreRGRB7": false, + "ControllerCoreRGRB8": false, + "ControllerCoreRGRB9": false, + "ControllerCoreRGRtFAWBInClkCycles": 27, + "ControllerCoreRGRtRASBInClkCycles": 20, + "ControllerCoreRGRtRCBInClkCycles": 27, + "ControllerCoreRGRtRPBInClkCycles": 8, + "ControllerCoreRGRtRRDB_LInClkCycles": 6, + "ControllerCoreRGRtRRDB_SInClkCycles": 6, + "ControllerCoreRefDisable": 0, + "ControllerCoreRefNumARCmdsIntREFI": 8192, + "DatabaseRecording": true, + "Debug": false, + "EnableWindowing": true, + "NumberOfDevicesOnDIMM": 4, + "NumberOfMemChannels": 1, + "PowerAnalysis": true, "SimulationName": "orgr_4b_std_timings", - "SimulationProgressBar": "1", - "ThermalSimulation": "0", - "UseMalloc": "0", - "WindowSize": "1000" + "SimulationProgressBar": true, + "ThermalSimulation": false, + "UseMalloc": false, + "WindowSize": 1000 } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/simulator/orgr_8b_opt_timings_ddr3.json b/DRAMSys/library/resources/configs/simulator/orgr_8b_opt_timings_ddr3.json index 6ea0f23d..0f8628a7 100644 --- a/DRAMSys/library/resources/configs/simulator/orgr_8b_opt_timings_ddr3.json +++ b/DRAMSys/library/resources/configs/simulator/orgr_8b_opt_timings_ddr3.json @@ -1,40 +1,40 @@ { "simconfig": { - "ControllerCoreRGR": "1", - "ControllerCoreRGRB0": "1", - "ControllerCoreRGRB1": "1", - "ControllerCoreRGRB10": "0", - "ControllerCoreRGRB11": "0", - "ControllerCoreRGRB12": "0", - "ControllerCoreRGRB13": "0", - "ControllerCoreRGRB14": "0", - "ControllerCoreRGRB15": "0", - "ControllerCoreRGRB2": "1", - "ControllerCoreRGRB3": "1", - "ControllerCoreRGRB4": "1", - "ControllerCoreRGRB5": "1", - "ControllerCoreRGRB6": "1", - "ControllerCoreRGRB7": "1", - "ControllerCoreRGRB8": "0", - "ControllerCoreRGRB9": "0", - "ControllerCoreRGRtFAWBInClkCycles": "0", - "ControllerCoreRGRtRASBInClkCycles": "11", - "ControllerCoreRGRtRCBInClkCycles": "16", - "ControllerCoreRGRtRPBInClkCycles": "5", - "ControllerCoreRGRtRRDB_LInClkCycles": "2", - "ControllerCoreRGRtRRDB_SInClkCycles": "2", - "ControllerCoreRefDisable": "0", - "ControllerCoreRefNumARCmdsIntREFI": "8192", - "DatabaseRecording": "1", - "Debug": "0", - "EnableWindowing": "1", - "NumberOfDevicesOnDIMM": "4", - "NumberOfMemChannels": "1", - "PowerAnalysis": "1", + "ControllerCoreRGR": true, + "ControllerCoreRGRB0": true, + "ControllerCoreRGRB1": true, + "ControllerCoreRGRB10": false, + "ControllerCoreRGRB11": false, + "ControllerCoreRGRB12": false, + "ControllerCoreRGRB13": false, + "ControllerCoreRGRB14": false, + "ControllerCoreRGRB15": false, + "ControllerCoreRGRB2": true, + "ControllerCoreRGRB3": true, + "ControllerCoreRGRB4": true, + "ControllerCoreRGRB5": true, + "ControllerCoreRGRB6": true, + "ControllerCoreRGRB7": true, + "ControllerCoreRGRB8": false, + "ControllerCoreRGRB9": false, + "ControllerCoreRGRtFAWBInClkCycles": 0, + "ControllerCoreRGRtRASBInClkCycles": 11, + "ControllerCoreRGRtRCBInClkCycles": 16, + "ControllerCoreRGRtRPBInClkCycles": 5, + "ControllerCoreRGRtRRDB_LInClkCycles": 2, + "ControllerCoreRGRtRRDB_SInClkCycles": 2, + "ControllerCoreRefDisable": 0, + "ControllerCoreRefNumARCmdsIntREFI": 8192, + "DatabaseRecording": true, + "Debug": false, + "EnableWindowing": true, + "NumberOfDevicesOnDIMM": 4, + "NumberOfMemChannels": 1, + "PowerAnalysis": true, "SimulationName": "orgr_8b_opt_timings", - "SimulationProgressBar": "1", - "ThermalSimulation": "0", - "UseMalloc": "0", - "WindowSize": "1000" + "SimulationProgressBar": true, + "ThermalSimulation": false, + "UseMalloc": false, + "WindowSize": 1000 } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/simulator/orgr_8b_std_timings_ddr3.json b/DRAMSys/library/resources/configs/simulator/orgr_8b_std_timings_ddr3.json index 8fcf3d30..f382d2a3 100644 --- a/DRAMSys/library/resources/configs/simulator/orgr_8b_std_timings_ddr3.json +++ b/DRAMSys/library/resources/configs/simulator/orgr_8b_std_timings_ddr3.json @@ -1,42 +1,40 @@ { "simconfig": { - "ControllerCoreRGR": { - "@value": "1" - }, - "ControllerCoreRGRB0": "1", - "ControllerCoreRGRB1": "1", - "ControllerCoreRGRB10": "0", - "ControllerCoreRGRB11": "0", - "ControllerCoreRGRB12": "0", - "ControllerCoreRGRB13": "0", - "ControllerCoreRGRB14": "0", - "ControllerCoreRGRB15": "0", - "ControllerCoreRGRB2": "1", - "ControllerCoreRGRB3": "1", - "ControllerCoreRGRB4": "1", - "ControllerCoreRGRB5": "1", - "ControllerCoreRGRB6": "1", - "ControllerCoreRGRB7": "1", - "ControllerCoreRGRB8": "0", - "ControllerCoreRGRB9": "0", - "ControllerCoreRGRtFAWBInClkCycles": "27", - "ControllerCoreRGRtRASBInClkCycles": "20", - "ControllerCoreRGRtRCBInClkCycles": "27", - "ControllerCoreRGRtRPBInClkCycles": "8", - "ControllerCoreRGRtRRDB_LInClkCycles": "6", - "ControllerCoreRGRtRRDB_SInClkCycles": "6", - "ControllerCoreRefDisable": "0", - "ControllerCoreRefNumARCmdsIntREFI": "8192", - "DatabaseRecording": "1", - "Debug": "0", - "EnableWindowing": "1", - "NumberOfDevicesOnDIMM": "4", - "NumberOfMemChannels": "1", - "PowerAnalysis": "1", + "ControllerCoreRGR": true, + "ControllerCoreRGRB0": true, + "ControllerCoreRGRB1": true, + "ControllerCoreRGRB10": false, + "ControllerCoreRGRB11": false, + "ControllerCoreRGRB12": false, + "ControllerCoreRGRB13": false, + "ControllerCoreRGRB14": false, + "ControllerCoreRGRB15": false, + "ControllerCoreRGRB2": true, + "ControllerCoreRGRB3": true, + "ControllerCoreRGRB4": true, + "ControllerCoreRGRB5": true, + "ControllerCoreRGRB6": true, + "ControllerCoreRGRB7": true, + "ControllerCoreRGRB8": false, + "ControllerCoreRGRB9": false, + "ControllerCoreRGRtFAWBInClkCycles": 27, + "ControllerCoreRGRtRASBInClkCycles": 20, + "ControllerCoreRGRtRCBInClkCycles": 27, + "ControllerCoreRGRtRPBInClkCycles": 8, + "ControllerCoreRGRtRRDB_LInClkCycles": 6, + "ControllerCoreRGRtRRDB_SInClkCycles": 6, + "ControllerCoreRefDisable": 0, + "ControllerCoreRefNumARCmdsIntREFI": 8192, + "DatabaseRecording": true, + "Debug": false, + "EnableWindowing": true, + "NumberOfDevicesOnDIMM": 4, + "NumberOfMemChannels": 1, + "PowerAnalysis": true, "SimulationName": "orgr_8b_std_timings_ddr3", - "SimulationProgressBar": "1", - "ThermalSimulation": "0", - "UseMalloc": "0", - "WindowSize": "1000" + "SimulationProgressBar": true, + "ThermalSimulation": false, + "UseMalloc": false, + "WindowSize": 1000 } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/simulator/orgr_ddr4.json b/DRAMSys/library/resources/configs/simulator/orgr_ddr4.json index e765f2db..d8b257da 100644 --- a/DRAMSys/library/resources/configs/simulator/orgr_ddr4.json +++ b/DRAMSys/library/resources/configs/simulator/orgr_ddr4.json @@ -1,21 +1,21 @@ { "simconfig": { - "AddressOffset": "0", - "CheckTLM2Protocol": "0", - "DatabaseRecording": "1", - "Debug": "0", + "AddressOffset": 0, + "CheckTLM2Protocol": false, + "DatabaseRecording": true, + "Debug": false, "ECCControllerMode": "Disabled", - "EnableWindowing": "1", + "EnableWindowing": true, "ErrorCSVFile": "", - "ErrorChipSeed": "42", - "NumberOfDevicesOnDIMM": "4", - "NumberOfMemChannels": "1", - "PowerAnalysis": "1", + "ErrorChipSeed": 42, + "NumberOfDevicesOnDIMM": 4, + "NumberOfMemChannels": 1, + "PowerAnalysis": true, "SimulationName": "orgr_ddr4", - "SimulationProgressBar": "1", + "SimulationProgressBar": true, "StoreMode": "NoStorage", - "ThermalSimulation": "0", - "UseMalloc": "0", - "WindowSize": "1000" + "ThermalSimulation": false, + "UseMalloc": false, + "WindowSize": 1000 } } \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/simulator/rgrsimcfg-gem5-fs.json b/DRAMSys/library/resources/configs/simulator/rgrsimcfg-gem5-fs.json index eed5e991..a1d40c8a 100644 --- a/DRAMSys/library/resources/configs/simulator/rgrsimcfg-gem5-fs.json +++ b/DRAMSys/library/resources/configs/simulator/rgrsimcfg-gem5-fs.json @@ -1,21 +1,21 @@ { "simconfig": { - "AddressOffset": "2147483648", - "CheckTLM2Protocol": "0", - "DatabaseRecording": "0", - "Debug": "0", + "AddressOffset": 2147483648, + "CheckTLM2Protocol": false, + "DatabaseRecording": false, + "Debug": false, "ECCControllerMode": "Disabled", - "EnableWindowing": "1", + "EnableWindowing": true, "ErrorCSVFile": "", - "ErrorChipSeed": "42", - "NumberOfDevicesOnDIMM": "4", - "NumberOfMemChannels": "1", - "PowerAnalysis": "1", + "ErrorChipSeed": 42, + "NumberOfDevicesOnDIMM": 4, + "NumberOfMemChannels": 1, + "PowerAnalysis": true, "SimulationName": "rgr", - "SimulationProgressBar": "1", + "SimulationProgressBar": true, "StoreMode": "Store", - "ThermalSimulation": "0", - "UseMalloc": "1", - "WindowSize": "1000" + "ThermalSimulation": false, + "UseMalloc": true, + "WindowSize": 1000 } } \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/simulator/rgrsimcfg-gem5-se.json b/DRAMSys/library/resources/configs/simulator/rgrsimcfg-gem5-se.json index 56e35f21..f02a1f7a 100644 --- a/DRAMSys/library/resources/configs/simulator/rgrsimcfg-gem5-se.json +++ b/DRAMSys/library/resources/configs/simulator/rgrsimcfg-gem5-se.json @@ -1,21 +1,21 @@ { "simconfig": { - "AddressOffset": "0", - "CheckTLM2Protocol": "0", - "DatabaseRecording": "1", - "Debug": "0", + "AddressOffset": 0, + "CheckTLM2Protocol": false, + "DatabaseRecording": true, + "Debug": false, "ECCControllerMode": "Disabled", - "EnableWindowing": "1", + "EnableWindowing": true, "ErrorCSVFile": "", - "ErrorChipSeed": "42", - "NumberOfDevicesOnDIMM": "4", - "NumberOfMemChannels": "1", - "PowerAnalysis": "1", + "ErrorChipSeed": 42, + "NumberOfDevicesOnDIMM": 4, + "NumberOfMemChannels": 1, + "PowerAnalysis": true, "SimulationName": "rgr", - "SimulationProgressBar": "1", + "SimulationProgressBar": true, "StoreMode": "Store", - "ThermalSimulation": "0", - "UseMalloc": "0", - "WindowSize": "1000" + "ThermalSimulation": false, + "UseMalloc": false, + "WindowSize": 1000 } } \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/simulator/rgrsimcfg.json b/DRAMSys/library/resources/configs/simulator/rgrsimcfg.json index 9eed055c..8b538820 100644 --- a/DRAMSys/library/resources/configs/simulator/rgrsimcfg.json +++ b/DRAMSys/library/resources/configs/simulator/rgrsimcfg.json @@ -1,21 +1,21 @@ { "simconfig": { - "AddressOffset": "0", - "CheckTLM2Protocol": "0", - "DatabaseRecording": "1", - "Debug": "0", + "AddressOffset": 0, + "CheckTLM2Protocol": false, + "DatabaseRecording": true, + "Debug": false, "ECCControllerMode": "Disabled", - "EnableWindowing": "1", + "EnableWindowing": true, "ErrorCSVFile": "", - "ErrorChipSeed": "42", - "NumberOfDevicesOnDIMM": "4", - "NumberOfMemChannels": "1", - "PowerAnalysis": "1", + "ErrorChipSeed": 42, + "NumberOfDevicesOnDIMM": 4, + "NumberOfMemChannels": 1, + "PowerAnalysis": true, "SimulationName": "rgr", - "SimulationProgressBar": "1", + "SimulationProgressBar": true, "StoreMode": "NoStorage", - "ThermalSimulation": "0", - "UseMalloc": "0", - "WindowSize": "1000" + "ThermalSimulation": false, + "UseMalloc": false, + "WindowSize": 1000 } } \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/simulator/sms.json b/DRAMSys/library/resources/configs/simulator/sms.json index 35dea1cf..b0d9f3d4 100644 --- a/DRAMSys/library/resources/configs/simulator/sms.json +++ b/DRAMSys/library/resources/configs/simulator/sms.json @@ -1,16 +1,16 @@ { "simconfig": { - "CheckTLM2Protocol": "0", - "DatabaseRecording": "1", - "Debug": "0", - "EnableWindowing": "1", - "NumberOfDevicesOnDIMM": "1", - "NumberOfMemChannels": "4", - "PowerAnalysis": "1", + "CheckTLM2Protocol": false, + "DatabaseRecording": true, + "Debug": false, + "EnableWindowing": true, + "NumberOfDevicesOnDIMM": 1, + "NumberOfMemChannels": 4, + "PowerAnalysis": true, "SimulationName": "sms", - "SimulationProgressBar": "1", - "ThermalSimulation": "0", - "UseMalloc": "0", - "WindowSize": "1000" + "SimulationProgressBar": true, + "ThermalSimulation": false, + "UseMalloc": false, + "WindowSize": 1000 } } \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/simulator/wideio.json b/DRAMSys/library/resources/configs/simulator/wideio.json index 35551829..4a0bd0ee 100644 --- a/DRAMSys/library/resources/configs/simulator/wideio.json +++ b/DRAMSys/library/resources/configs/simulator/wideio.json @@ -1,20 +1,20 @@ { "simconfig": { - "CheckTLM2Protocol": "0", - "DatabaseRecording": "1", - "Debug": "0", + "CheckTLM2Protocol": false, + "DatabaseRecording": true, + "Debug": false, "ECCControllerMode": "Disabled", - "EnableWindowing": "1", + "EnableWindowing": true, "ErrorCSVFile": "../../DRAMSys/library/resources/error/wideio.csv", - "ErrorChipSeed": "42", - "NumberOfDevicesOnDIMM": "1", - "NumberOfMemChannels": "4", - "PowerAnalysis": "1", + "ErrorChipSeed": 42, + "NumberOfDevicesOnDIMM": 1, + "NumberOfMemChannels": 4, + "PowerAnalysis": true, "SimulationName": "wideio", - "SimulationProgressBar": "1", + "SimulationProgressBar": true, "StoreMode": "NoStorage", - "ThermalSimulation": "0", - "UseMalloc": "0", - "WindowSize": "1000" + "ThermalSimulation": false, + "UseMalloc": false, + "WindowSize": 1000 } } \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/simulator/wideio_ecc.json b/DRAMSys/library/resources/configs/simulator/wideio_ecc.json index b664a326..216d3623 100644 --- a/DRAMSys/library/resources/configs/simulator/wideio_ecc.json +++ b/DRAMSys/library/resources/configs/simulator/wideio_ecc.json @@ -1,20 +1,20 @@ { "simconfig": { - "CheckTLM2Protocol": "0", - "DatabaseRecording": "1", - "Debug": "0", + "CheckTLM2Protocol": false, + "DatabaseRecording": true, + "Debug": false, "ECCControllerMode": "Hamming", - "EnableWindowing": "1", + "EnableWindowing": true, "ErrorCSVFile": "../../DRAMSys/library/resources/error/wideio.csv", - "ErrorChipSeed": "42", - "NumberOfDevicesOnDIMM": "1", - "NumberOfMemChannels": "1", - "PowerAnalysis": "1", + "ErrorChipSeed": 42, + "NumberOfDevicesOnDIMM": 1, + "NumberOfMemChannels": 1, + "PowerAnalysis": true, "SimulationName": "wideio_ecc", - "SimulationProgressBar": "1", + "SimulationProgressBar": true, "StoreMode": "ErrorModel", - "ThermalSimulation": "0", - "UseMalloc": "0", - "WindowSize": "1000" + "ThermalSimulation": false, + "UseMalloc": false, + "WindowSize": 1000 } } \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/simulator/wideio_thermal.json b/DRAMSys/library/resources/configs/simulator/wideio_thermal.json index d4fa0fd7..6946a7e4 100644 --- a/DRAMSys/library/resources/configs/simulator/wideio_thermal.json +++ b/DRAMSys/library/resources/configs/simulator/wideio_thermal.json @@ -1,20 +1,20 @@ { "simconfig": { - "CheckTLM2Protocol": "0", - "DatabaseRecording": "1", - "Debug": "0", + "CheckTLM2Protocol": false, + "DatabaseRecording": true, + "Debug": false, "ECCControllerMode": "Disabled", - "EnableWindowing": "1", + "EnableWindowing": true, "ErrorCSVFile": "../../DRAMSys/library/resources/error/wideio.csv", - "ErrorChipSeed": "42", - "NumberOfDevicesOnDIMM": "1", - "NumberOfMemChannels": "1", - "PowerAnalysis": "1", + "ErrorChipSeed": 42, + "NumberOfDevicesOnDIMM": 1, + "NumberOfMemChannels": 1, + "PowerAnalysis": true, "SimulationName": "wideio", - "SimulationProgressBar": "1", + "SimulationProgressBar": true, "StoreMode": "NoStorage", - "ThermalSimulation": "1", - "UseMalloc": "0", - "WindowSize": "1000" + "ThermalSimulation": true, + "UseMalloc": false, + "WindowSize": 1000 } } \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/thermalsim/config.json b/DRAMSys/library/resources/configs/thermalsim/config.json index 03064d1b..b88ed84c 100644 --- a/DRAMSys/library/resources/configs/thermalsim/config.json +++ b/DRAMSys/library/resources/configs/thermalsim/config.json @@ -1,15 +1,15 @@ { "thermalsimconfig": { "TemperatureScale": "Celsius", - "StaticTemperatureDefaultValue": "89", - "ThermalSimPeriod":"100", + "StaticTemperatureDefaultValue": 89, + "ThermalSimPeriod":100, "ThermalSimUnit":"us", "PowerInfoFile": "powerInfo.json", "IceServerIp": "127.0.0.1", - "IceServerPort": "11880", - "SimPeriodAdjustFactor" : "10", - "NPowStableCyclesToIncreasePeriod": "5", - "GenerateTemperatureMap": "1", - "GeneratePowerMap": "1" + "IceServerPort": 11880, + "SimPeriodAdjustFactor" : 10, + "NPowStableCyclesToIncreasePeriod": 5, + "GenerateTemperatureMap": true, + "GeneratePowerMap": true } } diff --git a/DRAMSys/library/resources/configs/thermalsim/powerInfo.json b/DRAMSys/library/resources/configs/thermalsim/powerInfo.json index 80c12d8e..524f690f 100644 --- a/DRAMSys/library/resources/configs/thermalsim/powerInfo.json +++ b/DRAMSys/library/resources/configs/thermalsim/powerInfo.json @@ -1,20 +1,20 @@ { "powerInfo": { "dram_die_channel0": { - "init_pow": "0", - "threshold": "1.0" + "init_pow": 0, + "threshold": 1.0 }, "dram_die_channel1": { - "init_pow": "0", - "threshold": "1.0" + "init_pow": 0, + "threshold": 1.0 }, "dram_die_channel2": { - "init_pow": "0", - "threshold": "1.0" + "init_pow": 0, + "threshold": 1.0 }, "dram_die_channel3": { - "init_pow": "0", - "threshold": "1.0" + "init_pow": 0, + "threshold": 1.0 } } } diff --git a/DRAMSys/library/resources/simulations/ddr3-ecc.json b/DRAMSys/library/resources/simulations/ddr3-ecc.json index 410e000b..bb0a6769 100644 --- a/DRAMSys/library/resources/simulations/ddr3-ecc.json +++ b/DRAMSys/library/resources/simulations/ddr3-ecc.json @@ -8,9 +8,9 @@ "thermalconfig": "config.xml", "tracesetup": [ { - "clkMhz": "1000", + "clkMhz": 1000, "name": "test_ecc.stl" } ] } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/simulations/ddr3-example.json b/DRAMSys/library/resources/simulations/ddr3-example.json index 9f14b26c..41565198 100644 --- a/DRAMSys/library/resources/simulations/ddr3-example.json +++ b/DRAMSys/library/resources/simulations/ddr3-example.json @@ -8,9 +8,9 @@ "thermalconfig": "config.json", "tracesetup": [ { - "clkMhz": "800", + "clkMhz": 800, "name": "ddr3_example.stl" } ] } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/simulations/ddr3-example2.json b/DRAMSys/library/resources/simulations/ddr3-example2.json index d3f06fa8..152fe432 100644 --- a/DRAMSys/library/resources/simulations/ddr3-example2.json +++ b/DRAMSys/library/resources/simulations/ddr3-example2.json @@ -8,13 +8,13 @@ "thermalconfig": "config.xml", "tracesetup": [ { - "clkMhz": "300", + "clkMhz": 300, "name": "ddr3_example.stl" }, { - "clkMhz": "400", + "clkMhz": 400, "name": "ddr3_example.stl" } ] } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/simulations/ddr3-single-device.json b/DRAMSys/library/resources/simulations/ddr3-single-device.json index 1cbd05f9..f0e5ad25 100644 --- a/DRAMSys/library/resources/simulations/ddr3-single-device.json +++ b/DRAMSys/library/resources/simulations/ddr3-single-device.json @@ -8,9 +8,9 @@ "thermalconfig": "config.xml", "tracesetup": [ { - "clkMhz": "200", + "clkMhz": 200, "name": "ddr3_single_dev_example.stl" } ] } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/simulations/ddr3_postpone_ref_test.json b/DRAMSys/library/resources/simulations/ddr3_postpone_ref_test.json index c8eaf32d..0dfa7938 100644 --- a/DRAMSys/library/resources/simulations/ddr3_postpone_ref_test.json +++ b/DRAMSys/library/resources/simulations/ddr3_postpone_ref_test.json @@ -8,9 +8,9 @@ "thermalconfig": "config.xml", "tracesetup": [ { - "clkMhz": "1000", + "clkMhz": 1000, "name": "ddr3_postpone_ref_test_1.stl" } ] } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/simulations/ddr4-example.json b/DRAMSys/library/resources/simulations/ddr4-example.json index 4ce02606..839cd6e1 100644 --- a/DRAMSys/library/resources/simulations/ddr4-example.json +++ b/DRAMSys/library/resources/simulations/ddr4-example.json @@ -8,9 +8,9 @@ "thermalconfig": "config.xml", "tracesetup": [ { - "clkMhz": "200", + "clkMhz": 200, "name": "ddr3_example.stl" } ] } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/simulations/hbm2-example.json b/DRAMSys/library/resources/simulations/hbm2-example.json index e1826e17..43462abd 100644 --- a/DRAMSys/library/resources/simulations/hbm2-example.json +++ b/DRAMSys/library/resources/simulations/hbm2-example.json @@ -8,9 +8,9 @@ "thermalconfig": "config.xml", "tracesetup": [ { - "clkMhz": "1000", + "clkMhz": 1000, "name": "ddr3_example.stl" } ] } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/simulations/lpddr4-example.json b/DRAMSys/library/resources/simulations/lpddr4-example.json index 506fe427..488b6056 100644 --- a/DRAMSys/library/resources/simulations/lpddr4-example.json +++ b/DRAMSys/library/resources/simulations/lpddr4-example.json @@ -8,9 +8,9 @@ "thermalconfig": "config.xml", "tracesetup": [ { - "clkMhz": "200", + "clkMhz": 200, "name": "ddr3_example.stl" } ] } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/simulations/ranktest.json b/DRAMSys/library/resources/simulations/ranktest.json index 36dc5544..4089493f 100644 --- a/DRAMSys/library/resources/simulations/ranktest.json +++ b/DRAMSys/library/resources/simulations/ranktest.json @@ -8,9 +8,9 @@ "thermalconfig": "config.xml", "tracesetup": [ { - "clkMhz": "200", + "clkMhz": 200, "name": "ranktest.stl" } ] } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/simulations/rgrsim.json b/DRAMSys/library/resources/simulations/rgrsim.json index 7c6955f8..8384dc96 100644 --- a/DRAMSys/library/resources/simulations/rgrsim.json +++ b/DRAMSys/library/resources/simulations/rgrsim.json @@ -8,9 +8,9 @@ "thermalconfig": "config.xml", "tracesetup": [ { - "clkMhz": "1000", + "clkMhz": 1000, "name": "1_720x1280_64-Pixelgroesse_imb3_str1_scram_ddr4_8b_same_clock.stl" } ] } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/simulations/sms-example.json b/DRAMSys/library/resources/simulations/sms-example.json index ababf58f..e4c6bfd9 100644 --- a/DRAMSys/library/resources/simulations/sms-example.json +++ b/DRAMSys/library/resources/simulations/sms-example.json @@ -8,17 +8,17 @@ "thermalconfig": "config.xml", "tracesetup": [ { - "clkMhz": "1000", + "clkMhz": 1000, "name": "random.stl" }, { - "clkMhz": "1000", + "clkMhz": 1000, "name": "chstone-adpcm_32.stl" }, { - "clkMhz": "1000", + "clkMhz": 1000, "name": "stream.stl" } ] } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/simulations/wideio-ecc.json b/DRAMSys/library/resources/simulations/wideio-ecc.json index 7262b3e4..c3863267 100644 --- a/DRAMSys/library/resources/simulations/wideio-ecc.json +++ b/DRAMSys/library/resources/simulations/wideio-ecc.json @@ -8,9 +8,9 @@ "thermalconfig": "config.xml", "tracesetup": [ { - "clkMhz": "1000", + "clkMhz": 1000, "name": "test_ecc.stl" } ] } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/simulations/wideio-example.json b/DRAMSys/library/resources/simulations/wideio-example.json index f176953a..5f41c22a 100644 --- a/DRAMSys/library/resources/simulations/wideio-example.json +++ b/DRAMSys/library/resources/simulations/wideio-example.json @@ -8,9 +8,9 @@ "thermalconfig": "config.xml", "tracesetup": [ { - "clkMhz": "1000", + "clkMhz": 1000, "name": "chstone-adpcm_32.stl" } ] } -} \ No newline at end of file +} diff --git a/DRAMSys/library/src/configuration/Configuration.cpp b/DRAMSys/library/src/configuration/Configuration.cpp index 959b128f..ed947d5f 100644 --- a/DRAMSys/library/src/configuration/Configuration.cpp +++ b/DRAMSys/library/src/configuration/Configuration.cpp @@ -65,7 +65,7 @@ enum sc_time_unit string2TimeUnit(std::string s) } } -void Configuration::setParameter(std::string name, std::string value) +void Configuration::setParameter(std::string name, nlohmann::json value) { // MCConfig if (name == "PagePolicy") @@ -73,7 +73,7 @@ void Configuration::setParameter(std::string name, std::string value) else if (name == "Scheduler") scheduler = value; else if (name == "RequestBufferSize") - requestBufferSize = std::stoul(value); + requestBufferSize = value; else if (name == "CmdMux") cmdMux = value; else if (name == "RespQueue") @@ -81,43 +81,43 @@ void Configuration::setParameter(std::string name, std::string value) else if (name == "RefreshPolicy") refreshPolicy = value; else if (name == "RefreshMode") - refreshMode = std::stoul(value); + refreshMode = value; else if (name == "RefreshMaxPostponed") - refreshMaxPostponed = std::stoul(value); + refreshMaxPostponed = value; else if (name == "RefreshMaxPulledin") - refreshMaxPulledin = std::stoul(value); + refreshMaxPulledin = value; else if (name == "PowerDownPolicy") powerDownPolicy = value; else if (name == "PowerDownTimeout") - powerDownTimeout = std::stoul(value); + powerDownTimeout = value; //SimConfig------------------------------------------------ else if (name == "SimulationName") simulationName = value; else if (name == "DatabaseRecording") - databaseRecording = std::stoul(value); + databaseRecording = value; else if (name == "PowerAnalysis") - powerAnalysis = std::stoul(value); + powerAnalysis = value; else if (name == "EnableWindowing") - enableWindowing = std::stoul(value); + enableWindowing = value; else if (name == "WindowSize") { - windowSize = std::stoul(value); + windowSize = value; if (windowSize == 0) SC_REPORT_FATAL("Configuration", ("Invalid value for parameter " + name + ". This parameter must be at least one.").c_str()); } else if (name == "Debug") - debug = std::stoul(value); + debug = value; else if (name == "NumberOfMemChannels") - numberOfMemChannels = std::stoul(value); + numberOfMemChannels = value; else if (name == "ThermalSimulation") - thermalSimulation = std::stoul(value); + thermalSimulation = value; else if (name == "SimulationProgressBar") - simulationProgressBar = std::stoul(value); + simulationProgressBar = value; else if (name == "NumberOfDevicesOnDIMM") { - numberOfDevicesOnDIMM = std::stoul(value); + numberOfDevicesOnDIMM = value; if (numberOfDevicesOnDIMM == 0) SC_REPORT_FATAL("Configuration", ("Invalid value for parameter " + name + @@ -126,20 +126,20 @@ void Configuration::setParameter(std::string name, std::string value) else if (name == "AddressOffset") { #ifdef DRAMSYS_GEM5 - addressOffset = std::stoull(value); + addressOffset = value; #else addressOffset = 0; #endif } else if (name == "UseMalloc") - useMalloc = std::stoul(value); + useMalloc = value; else if (name == "CheckTLM2Protocol") - checkTLM2Protocol = std::stoul(value); + checkTLM2Protocol = value; else if (name == "ECCControllerMode") ECCMode = value; // Specification for ErrorChipSeed, ErrorCSVFile path and StoreMode else if (name == "ErrorChipSeed") - errorChipSeed = std::stoul(value); + errorChipSeed = value; else if (name == "ErrorCSVFile") errorCSVFile = value; else if (name == "StoreMode") @@ -153,9 +153,9 @@ void Configuration::setParameter(std::string name, std::string value) temperatureSim.TemperatureScale = value; } else if (name == "StaticTemperatureDefaultValue") - temperatureSim.StaticTemperatureDefaultValue = std::stoi(value); + temperatureSim.StaticTemperatureDefaultValue = value; else if (name == "ThermalSimPeriod") - temperatureSim.ThermalSimPeriod = std::stod(value.c_str()); + temperatureSim.ThermalSimPeriod = value; else if (name == "ThermalSimUnit") temperatureSim.ThermalSimUnit = string2TimeUnit(value); else if (name == "PowerInfoFile") @@ -166,15 +166,15 @@ void Configuration::setParameter(std::string name, std::string value) else if (name == "IceServerIp") temperatureSim.IceServerIp = value; else if (name == "IceServerPort") - temperatureSim.IceServerPort = std::stoul(value); + temperatureSim.IceServerPort = value; else if (name == "SimPeriodAdjustFactor") - temperatureSim.SimPeriodAdjustFactor = std::stoi(value.c_str()); + temperatureSim.SimPeriodAdjustFactor = value; else if (name == "NPowStableCyclesToIncreasePeriod") - temperatureSim.NPowStableCyclesToIncreasePeriod = std::stoi(value.c_str()); + temperatureSim.NPowStableCyclesToIncreasePeriod = value; else if (name == "GenerateTemperatureMap") - temperatureSim.GenerateTemperatureMap = std::stoul(value); + temperatureSim.GenerateTemperatureMap = value; else if (name == "GeneratePowerMap") - temperatureSim.GeneratePowerMap = std::stoul(value); + temperatureSim.GeneratePowerMap = value; else SC_REPORT_FATAL("Configuration", ("Parameter " + name + " not defined in Configuration").c_str()); diff --git a/DRAMSys/library/src/configuration/Configuration.h b/DRAMSys/library/src/configuration/Configuration.h index a228316f..40529f6d 100644 --- a/DRAMSys/library/src/configuration/Configuration.h +++ b/DRAMSys/library/src/configuration/Configuration.h @@ -91,7 +91,7 @@ struct Configuration // MemSpec (from DRAM-Power) MemSpec *memSpec; - void setParameter(std::string name, std::string value); + void setParameter(std::string name, nlohmann::json value); //Configs for Seed, csv file and StorageMode unsigned int errorChipSeed; diff --git a/DRAMSys/library/src/configuration/TemperatureSimConfig.h b/DRAMSys/library/src/configuration/TemperatureSimConfig.h index b540afd0..1c45a7e5 100644 --- a/DRAMSys/library/src/configuration/TemperatureSimConfig.h +++ b/DRAMSys/library/src/configuration/TemperatureSimConfig.h @@ -94,15 +94,14 @@ struct TemperatureSimConfig // Load initial power values for all devices auto value= it.value(); - std::string init_pow_str = value["init_pow"]; - float pow = std::stof(init_pow_str); + float pow = value["init_pow"]; powerInitialValues.push_back(pow); // Load power thresholds for all devices //Changes in power dissipation that exceed the threshods //will make the thermal simulation to be executed more often) - std::string thr_str = value["threshold"]; - float thr = std::stof(thr_str); + + float thr = value["threshold"]; powerThresholds.push_back(thr); } } diff --git a/README.md b/README.md index 6b5215e3..61ebaf6a 100644 --- a/README.md +++ b/README.md @@ -115,13 +115,12 @@ The compilation generates executable binary files **DRAMSys** and From the build directory use the commands below to execute DRAMSys. ```bash -$ cd simulator $ ./DRAMSys ``` To run DRAMSys with a specific config: ```bash -$ ./DRAMSys ../../DRAMSys/library/resources/simulations/ddr3-example.json +$ ./DRAMSys ../DRAMSys/library/resources/simulations/ddr3-example.json ``` To run DRAMSys with a specific config and a resource folder somewhere else to the standard: @@ -290,23 +289,23 @@ Below, the sub-configurations are listed and explained. ```json { "simconfig": { - "AddressOffset": "0", - "CheckTLM2Protocol": "0", - "DatabaseRecording": "1", - "Debug": "0", + "AddressOffset": 0, + "CheckTLM2Protocol": false, + "DatabaseRecording": true, + "Debug": false, "ECCControllerMode": "Disabled", - "EnableWindowing": "0", + "EnableWindowing": false, "ErrorCSVFile": "", - "ErrorChipSeed": "42", - "NumberOfDevicesOnDIMM": "8", - "NumberOfMemChannels": "1", - "PowerAnalysis": "0", + "ErrorChipSeed": 42, + "NumberOfDevicesOnDIMM": 8, + "NumberOfMemChannels": 1, + "PowerAnalysis": false, "SimulationName": "ddr3", - "SimulationProgressBar": "1", + "SimulationProgressBar": true, "StoreMode": "NoStorage", - "ThermalSimulation": "0", - "UseMalloc": "0", - "WindowSize": "1000" + "ThermalSimulation": false, + "UseMalloc": false, + "WindowSize": 1000 } } ``` @@ -314,44 +313,44 @@ Below, the sub-configurations are listed and explained. - *SimulationName* (boolean) - Give the name of the simulation for distingushing from other simulations. - *Debug* (boolean) - - "1": enables debug output on console - - "0": disables debug output + - true: enables debug output on console + - false: disables debug output - *DatabaseRecording* (boolean) - - "1": enables trace file recording for the trace analyser tool - - "0": disables trace file recording + - true: enables trace file recording for the trace analyser tool + - false: disables trace file recording - *PowerAnalysis* (boolean) - - "1": enables live power analysis with the DRAMPower tool - - "0": disables power analysis + - true: enables live power analysis with the DRAMPower tool + - false: disables power analysis - *EnableWindowing* (boolean) - - "1": enables temporal windowing - - "0": disables temporal windowing + - true: enables temporal windowing + - false: disables temporal windowing - *WindowSize* (unisgned int) - Size of the window in clock cycles used to evaluate average bandwidth and average power consumption - *NumberOfMemChannels* (unsigned int) - Number of memory channels - *ControllerCoreRefDisable* (boolean) - - "1": disables refreshes - - "0": normal operation (refreshes enabled) + - true: disables refreshes + - false: normal operation (refreshes enabled) - *ControllerCoreRGR* (boolean) - - "1": enable row granular refresh - - "0": normal operation + - true: enable row granular refresh + - false: normal operation - *ThermalSimulation* (boolean) - - "1": enables thermal simulation - - "0": static temperature during simulation + - true: enables thermal simulation + - false: static temperature during simulation - *SimulationProgressBar* (boolean) - - "1": enables the simulation progress bar - - "0": disables the simulation progress bar + - true: enables the simulation progress bar + - false: disables the simulation progress bar - *NumberOfDevicesOnDIMM* (unsigned int) - Number of devices on dual inline memory module - *CheckTLM2Protocol* (boolean) - - "1": enables the TLM-2.0 Protocol Checking - - "0": disables the TLM-2.0 Protocol Checking + - true: enables the TLM-2.0 Protocol Checking + - false: disables the TLM-2.0 Protocol Checking - *ECCControllerMode* (string) - "Disabled": No ECC Controller is used - "Hamming": Enables an ECC Controller with classic SECDED implementation using Hamming Code - *UseMalloc* (boolean) - - "0": model storage using mmap() (DEFAULT) - - "1": allocate memory for modeling storage using malloc() + - false: model storage using mmap() (DEFAULT) + - true: allocate memory for modeling storage using malloc() - **Temperature Simulator Configuration** @@ -363,21 +362,19 @@ Below, the sub-configurations are listed and explained. { "thermalsimconfig": { "TemperatureScale": "Celsius", - "StaticTemperatureDefaultValue": "89", - "ThermalSimPeriod":"100", + "StaticTemperatureDefaultValue": 89, + "ThermalSimPeriod":100, "ThermalSimUnit":"us", "PowerInfoFile": "powerInfo.json", "IceServerIp": "127.0.0.1", - "IceServerPort": "11880", - "SimPeriodAdjustFactor" : "10", - "NPowStableCyclesToIncreasePeriod": "5", - "GenerateTemperatureMap": "1", - "GeneratePowerMap": "1" + "IceServerPort": 11880, + "SimPeriodAdjustFactor" : 10, + "NPowStableCyclesToIncreasePeriod": 5, + "GenerateTemperatureMap": true, + "GeneratePowerMap": true } } ``` - The following types should be respected but written inside string quotes, not directly. - - *TemperatureScale* (string) - "Celsius" - "Fahrenheit" @@ -404,11 +401,11 @@ Below, the sub-configurations are listed and explained. - *NPowStableCyclesToIncreasePeriod* (unsigned int) - Wait this number of thermal simulation cycles with power stability (i.e., changes that do not exceed the thresholds) to start increasing the simulation period back to its configured value. - *GenerateTemperatureMap* (boolean) - - "1": generate temperature map files during thermal simulation - - "0": do not generate temperature map files during thermal simulation + - true: generate temperature map files during thermal simulation + - false: do not generate temperature map files during thermal simulation - *GeneratePowerMap* (boolean) - - "1": generate power map files during thermal simulation - - "0": do not generate power map files during thermal simulation + - true: generate power map files during thermal simulation + - false: do not generate power map files during thermal simulation - **Memory Specification** @@ -482,25 +479,25 @@ Below, the sub-configurations are listed and explained. "mcconfig": { "PagePolicy": "Open", "Scheduler": "Fifo", - "RequestBufferSize": "8", + "RequestBufferSize": 8, "CmdMux": "Oldest", "RespQueue": "Fifo", "RefreshPolicy": "Rankwise", - "RefreshMode": "1", - "RefreshMaxPostponed": "8", - "RefreshMaxPulledin": "8", + "RefreshMode": 1, + "RefreshMaxPostponed": 8, + "RefreshMaxPulledin": 8, "PowerDownPolicy": "NoPowerDown", - "PowerDownTimeout": "100" + "PowerDownTimeout": 100 } } ``` - *BankwiseLogic* (boolean) - - "1": perform bankwise-refresh [3] and bankwise-powerdown [4] - - "0": do not perform bankwise operations + - true: perform bankwise-refresh [3] and bankwise-powerdown [4] + - false: do not perform bankwise operations - *OpenPagePolicy* (boolean) - - "1": use open page precharge policy - - "0": do not use open page precharge policy + - true: use open page precharge policy + - false: do not use open page precharge policy - *MaxNrOfTransactions* (unsigned int) - Maximum number of transactions. - *Scheduler* (string) @@ -519,11 +516,11 @@ Below, the sub-configurations are listed and explained. - "TimeoutPDN": precharge idle - "TimeoutSREF": self refresh - *ReadWriteGrouping* (boolean) - - "1": enable read writing grouping - - "0": disable read writing grouping + - true: enable read writing grouping + - false: disable read writing grouping - *ReorderBuffer* (boolean) - - "1": use reordering buffer - - "0": do not use reordering buffer + - true: use reordering buffer + - false: do not use reordering buffer - *ErrorChipSeed* (unsigned int) - Seed to initialize the random error generator. - *ErrorCSVFile* (string) @@ -533,82 +530,82 @@ Below, the sub-configurations are listed and explained. - "Store": store data without error model - "ErrorModel": store data with error model [6] - *ControllerCoreRefDisable* (boolean) - - "1": disables refreshes - - "0": normal operation (refreshes enabled) + - true: disables refreshes + - false: normal operation (refreshes enabled) - ControllerCoreRefMode (unsigned int) - Refresh mode. 1: 1X, 2: 2X, 4: 4X. Refresh period is tREFI, tREFI/2, tREFI/4, respectively. Number of rows per refresh is affected. Maximum values for pull-in and postpone are affected. There are different values of tRFC for each mode that come from memory specifications. - *ControllerCoreRefForceMaxPostponeBurst* (boolean) - - "1": always postpone, resulting in a ControllerCoreRefMaxPostponed burst - - "0": normal operation + - true: always postpone, resulting in a ControllerCoreRefMaxPostponed burst + - false: normal operation - *ControllerCoreRefEnablePostpone* (boolean) - - "1": enables the postpone refresh feature - - "0": normal operation + - true: enables the postpone refresh feature + - false: normal operation - *ControllerCoreRefEnablePullIn* (boolean) - - "1": enables the pull-in refresh feature - - "0": normal operation + - true: enables the pull-in refresh feature + - false: normal operation - *ControllerCoreRefMaxPostponed* (unsigned int) - Max AR commands to be postponed. Refresh mode affects this config. - *ControllerCoreRefMaxPulledIn* (unsigned int) - Max AR commands to be pulled-in. Refresh mode affects this config. - *ControllerCoreRGR* (boolean) - - "1": enables row granular refresh feature (RGR) - - "0": normal operation + - true: enables row granular refresh feature (RGR) + - false: normal operation - *ControllerCoreRefNumARCmdsIntREFI* (unsigned int) - Number of AR commands to to be issued in a refresh period tREFI in 1X mode - *ControllerCoreRGRRowInc* (unsigned int) - Row increment for each AR command (selective refresh) - *ControllerCoreRGRB0* (boolean) - - "1": RGR this bank - - "0": skip this bank + - true: RGR this bank + - false: skip this bank - *ControllerCoreRGRB1* (boolean) - - "1": RGR this bank - - "0": skip this bank + - true: RGR this bank + - false: skip this bank - *ControllerCoreRGRB2* (boolean) - - "1": RGR this bank - - "0": skip this bank + - true: RGR this bank + - false: skip this bank - *ControllerCoreRGRB3* (boolean) - - "1": RGR this bank - - "0": skip this bank + - true: RGR this bank + - false: skip this bank - *ControllerCoreRGRB4* (boolean) - - "1": RGR this bank - - "0": skip this bank + - true: RGR this bank + - false: skip this bank - *ControllerCoreRGRB5* (boolean) - - "1": RGR this bank - - "0": skip this bank + - true: RGR this bank + - false: skip this bank - *ControllerCoreRGRB6* (boolean) - - "1": RGR this bank - - "0": skip this bank + - true: RGR this bank + - false: skip this bank - *ControllerCoreRGRB7* (boolean) - - "1": RGR this bank - - "0": skip this bank + - true: RGR this bank + - false: skip this bank - *ControllerCoreRGRB8* (boolean) - - "1": RGR this bank - - "0": skip this bank + - true: RGR this bank + - false: skip this bank - *ControllerCoreRGRB9* (boolean) - - "1": RGR this bank - - "0": skip this bank + - true: RGR this bank + - false: skip this bank - *ControllerCoreRGRB10* (boolean) - - "1": RGR this bank - - "0": skip this bank + - true: RGR this bank + - false: skip this bank - *ControllerCoreRGRB11* (boolean) - - "1": RGR this bank - - "0": skip this bank + - true: RGR this bank + - false: skip this bank - *ControllerCoreRGRB12* (boolean) - - "1": RGR this bank - - "0": skip this bank + - true: RGR this bank + - false: skip this bank - *ControllerCoreRGRB13* (boolean) - - "1": RGR this bank - - "0": skip this bank + - true: RGR this bank + - false: skip this bank - *ControllerCoreRGRB14* (boolean) - - "1": RGR this bank - - "0": skip this bank + - true: RGR this bank + - false: skip this bank - *ControllerCoreRGRB15* (boolean) - - "1": RGR this bank - - "0": skip this bank + - true: RGR this bank + - false: skip this bank - *ControllerCoreRGRtRASBInClkCycles* (unsigned int) - Timing can be changed to explore optimum row granular refresh (ORGR) - *ControllerCoreRGRtRRDB_LInClkCycles* (unsigned int)