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numbers and bools written without string quotes

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scorrea
2020-05-20 11:13:48 +02:00
parent b6f9c27722
commit efdfd7fc3d
44 changed files with 589 additions and 576 deletions
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README.md
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@@ -115,13 +115,12 @@ The compilation generates executable binary files **DRAMSys** and
From the build directory use the commands below to execute DRAMSys.
```bash
$ cd simulator
$ ./DRAMSys
```
To run DRAMSys with a specific config:
```bash
$ ./DRAMSys ../../DRAMSys/library/resources/simulations/ddr3-example.json
$ ./DRAMSys ../DRAMSys/library/resources/simulations/ddr3-example.json
```
To run DRAMSys with a specific config and a resource folder somewhere else to the standard:
@@ -290,23 +289,23 @@ Below, the sub-configurations are listed and explained.
```json
{
"simconfig": {
"AddressOffset": "0",
"CheckTLM2Protocol": "0",
"DatabaseRecording": "1",
"Debug": "0",
"AddressOffset": 0,
"CheckTLM2Protocol": false,
"DatabaseRecording": true,
"Debug": false,
"ECCControllerMode": "Disabled",
"EnableWindowing": "0",
"EnableWindowing": false,
"ErrorCSVFile": "",
"ErrorChipSeed": "42",
"NumberOfDevicesOnDIMM": "8",
"NumberOfMemChannels": "1",
"PowerAnalysis": "0",
"ErrorChipSeed": 42,
"NumberOfDevicesOnDIMM": 8,
"NumberOfMemChannels": 1,
"PowerAnalysis": false,
"SimulationName": "ddr3",
"SimulationProgressBar": "1",
"SimulationProgressBar": true,
"StoreMode": "NoStorage",
"ThermalSimulation": "0",
"UseMalloc": "0",
"WindowSize": "1000"
"ThermalSimulation": false,
"UseMalloc": false,
"WindowSize": 1000
}
}
```
@@ -314,44 +313,44 @@ Below, the sub-configurations are listed and explained.
- *SimulationName* (boolean)
- Give the name of the simulation for distingushing from other simulations.
- *Debug* (boolean)
- "1": enables debug output on console
- "0": disables debug output
- true: enables debug output on console
- false: disables debug output
- *DatabaseRecording* (boolean)
- "1": enables trace file recording for the trace analyser tool
- "0": disables trace file recording
- true: enables trace file recording for the trace analyser tool
- false: disables trace file recording
- *PowerAnalysis* (boolean)
- "1": enables live power analysis with the DRAMPower tool
- "0": disables power analysis
- true: enables live power analysis with the DRAMPower tool
- false: disables power analysis
- *EnableWindowing* (boolean)
- "1": enables temporal windowing
- "0": disables temporal windowing
- true: enables temporal windowing
- false: disables temporal windowing
- *WindowSize* (unisgned int)
- Size of the window in clock cycles used to evaluate average bandwidth and average power consumption
- *NumberOfMemChannels* (unsigned int)
- Number of memory channels
- *ControllerCoreRefDisable* (boolean)
- "1": disables refreshes
- "0": normal operation (refreshes enabled)
- true: disables refreshes
- false: normal operation (refreshes enabled)
- *ControllerCoreRGR* (boolean)
- "1": enable row granular refresh
- "0": normal operation
- true: enable row granular refresh
- false: normal operation
- *ThermalSimulation* (boolean)
- "1": enables thermal simulation
- "0": static temperature during simulation
- true: enables thermal simulation
- false: static temperature during simulation
- *SimulationProgressBar* (boolean)
- "1": enables the simulation progress bar
- "0": disables the simulation progress bar
- true: enables the simulation progress bar
- false: disables the simulation progress bar
- *NumberOfDevicesOnDIMM* (unsigned int)
- Number of devices on dual inline memory module
- *CheckTLM2Protocol* (boolean)
- "1": enables the TLM-2.0 Protocol Checking
- "0": disables the TLM-2.0 Protocol Checking
- true: enables the TLM-2.0 Protocol Checking
- false: disables the TLM-2.0 Protocol Checking
- *ECCControllerMode* (string)
- "Disabled": No ECC Controller is used
- "Hamming": Enables an ECC Controller with classic SECDED implementation using Hamming Code
- *UseMalloc* (boolean)
- "0": model storage using mmap() (DEFAULT)
- "1": allocate memory for modeling storage using malloc()
- false: model storage using mmap() (DEFAULT)
- true: allocate memory for modeling storage using malloc()
- **Temperature Simulator Configuration**
@@ -363,21 +362,19 @@ Below, the sub-configurations are listed and explained.
{
"thermalsimconfig": {
"TemperatureScale": "Celsius",
"StaticTemperatureDefaultValue": "89",
"ThermalSimPeriod":"100",
"StaticTemperatureDefaultValue": 89,
"ThermalSimPeriod":100,
"ThermalSimUnit":"us",
"PowerInfoFile": "powerInfo.json",
"IceServerIp": "127.0.0.1",
"IceServerPort": "11880",
"SimPeriodAdjustFactor" : "10",
"NPowStableCyclesToIncreasePeriod": "5",
"GenerateTemperatureMap": "1",
"GeneratePowerMap": "1"
"IceServerPort": 11880,
"SimPeriodAdjustFactor" : 10,
"NPowStableCyclesToIncreasePeriod": 5,
"GenerateTemperatureMap": true,
"GeneratePowerMap": true
}
}
```
The following types should be respected but written inside string quotes, not directly.
- *TemperatureScale* (string)
- "Celsius"
- "Fahrenheit"
@@ -404,11 +401,11 @@ Below, the sub-configurations are listed and explained.
- *NPowStableCyclesToIncreasePeriod* (unsigned int)
- Wait this number of thermal simulation cycles with power stability (i.e., changes that do not exceed the thresholds) to start increasing the simulation period back to its configured value.
- *GenerateTemperatureMap* (boolean)
- "1": generate temperature map files during thermal simulation
- "0": do not generate temperature map files during thermal simulation
- true: generate temperature map files during thermal simulation
- false: do not generate temperature map files during thermal simulation
- *GeneratePowerMap* (boolean)
- "1": generate power map files during thermal simulation
- "0": do not generate power map files during thermal simulation
- true: generate power map files during thermal simulation
- false: do not generate power map files during thermal simulation
- **Memory Specification**
@@ -482,25 +479,25 @@ Below, the sub-configurations are listed and explained.
"mcconfig": {
"PagePolicy": "Open",
"Scheduler": "Fifo",
"RequestBufferSize": "8",
"RequestBufferSize": 8,
"CmdMux": "Oldest",
"RespQueue": "Fifo",
"RefreshPolicy": "Rankwise",
"RefreshMode": "1",
"RefreshMaxPostponed": "8",
"RefreshMaxPulledin": "8",
"RefreshMode": 1,
"RefreshMaxPostponed": 8,
"RefreshMaxPulledin": 8,
"PowerDownPolicy": "NoPowerDown",
"PowerDownTimeout": "100"
"PowerDownTimeout": 100
}
}
```
- *BankwiseLogic* (boolean)
- "1": perform bankwise-refresh [3] and bankwise-powerdown [4]
- "0": do not perform bankwise operations
- true: perform bankwise-refresh [3] and bankwise-powerdown [4]
- false: do not perform bankwise operations
- *OpenPagePolicy* (boolean)
- "1": use open page precharge policy
- "0": do not use open page precharge policy
- true: use open page precharge policy
- false: do not use open page precharge policy
- *MaxNrOfTransactions* (unsigned int)
- Maximum number of transactions.
- *Scheduler* (string)
@@ -519,11 +516,11 @@ Below, the sub-configurations are listed and explained.
- "TimeoutPDN": precharge idle
- "TimeoutSREF": self refresh
- *ReadWriteGrouping* (boolean)
- "1": enable read writing grouping
- "0": disable read writing grouping
- true: enable read writing grouping
- false: disable read writing grouping
- *ReorderBuffer* (boolean)
- "1": use reordering buffer
- "0": do not use reordering buffer
- true: use reordering buffer
- false: do not use reordering buffer
- *ErrorChipSeed* (unsigned int)
- Seed to initialize the random error generator.
- *ErrorCSVFile* (string)
@@ -533,82 +530,82 @@ Below, the sub-configurations are listed and explained.
- "Store": store data without error model
- "ErrorModel": store data with error model [6]
- *ControllerCoreRefDisable* (boolean)
- "1": disables refreshes
- "0": normal operation (refreshes enabled)
- true: disables refreshes
- false: normal operation (refreshes enabled)
- ControllerCoreRefMode (unsigned int)
- Refresh mode. 1: 1X, 2: 2X, 4: 4X. Refresh period is tREFI, tREFI/2,
tREFI/4, respectively. Number of rows per refresh is affected. Maximum
values for pull-in and postpone are affected. There are different values
of tRFC for each mode that come from memory specifications.
- *ControllerCoreRefForceMaxPostponeBurst* (boolean)
- "1": always postpone, resulting in a ControllerCoreRefMaxPostponed burst
- "0": normal operation
- true: always postpone, resulting in a ControllerCoreRefMaxPostponed burst
- false: normal operation
- *ControllerCoreRefEnablePostpone* (boolean)
- "1": enables the postpone refresh feature
- "0": normal operation
- true: enables the postpone refresh feature
- false: normal operation
- *ControllerCoreRefEnablePullIn* (boolean)
- "1": enables the pull-in refresh feature
- "0": normal operation
- true: enables the pull-in refresh feature
- false: normal operation
- *ControllerCoreRefMaxPostponed* (unsigned int)
- Max AR commands to be postponed. Refresh mode affects this config.
- *ControllerCoreRefMaxPulledIn* (unsigned int)
- Max AR commands to be pulled-in. Refresh mode affects this config.
- *ControllerCoreRGR* (boolean)
- "1": enables row granular refresh feature (RGR)
- "0": normal operation
- true: enables row granular refresh feature (RGR)
- false: normal operation
- *ControllerCoreRefNumARCmdsIntREFI* (unsigned int)
- Number of AR commands to to be issued in a refresh period tREFI in 1X
mode
- *ControllerCoreRGRRowInc* (unsigned int)
- Row increment for each AR command (selective refresh)
- *ControllerCoreRGRB0* (boolean)
- "1": RGR this bank
- "0": skip this bank
- true: RGR this bank
- false: skip this bank
- *ControllerCoreRGRB1* (boolean)
- "1": RGR this bank
- "0": skip this bank
- true: RGR this bank
- false: skip this bank
- *ControllerCoreRGRB2* (boolean)
- "1": RGR this bank
- "0": skip this bank
- true: RGR this bank
- false: skip this bank
- *ControllerCoreRGRB3* (boolean)
- "1": RGR this bank
- "0": skip this bank
- true: RGR this bank
- false: skip this bank
- *ControllerCoreRGRB4* (boolean)
- "1": RGR this bank
- "0": skip this bank
- true: RGR this bank
- false: skip this bank
- *ControllerCoreRGRB5* (boolean)
- "1": RGR this bank
- "0": skip this bank
- true: RGR this bank
- false: skip this bank
- *ControllerCoreRGRB6* (boolean)
- "1": RGR this bank
- "0": skip this bank
- true: RGR this bank
- false: skip this bank
- *ControllerCoreRGRB7* (boolean)
- "1": RGR this bank
- "0": skip this bank
- true: RGR this bank
- false: skip this bank
- *ControllerCoreRGRB8* (boolean)
- "1": RGR this bank
- "0": skip this bank
- true: RGR this bank
- false: skip this bank
- *ControllerCoreRGRB9* (boolean)
- "1": RGR this bank
- "0": skip this bank
- true: RGR this bank
- false: skip this bank
- *ControllerCoreRGRB10* (boolean)
- "1": RGR this bank
- "0": skip this bank
- true: RGR this bank
- false: skip this bank
- *ControllerCoreRGRB11* (boolean)
- "1": RGR this bank
- "0": skip this bank
- true: RGR this bank
- false: skip this bank
- *ControllerCoreRGRB12* (boolean)
- "1": RGR this bank
- "0": skip this bank
- true: RGR this bank
- false: skip this bank
- *ControllerCoreRGRB13* (boolean)
- "1": RGR this bank
- "0": skip this bank
- true: RGR this bank
- false: skip this bank
- *ControllerCoreRGRB14* (boolean)
- "1": RGR this bank
- "0": skip this bank
- true: RGR this bank
- false: skip this bank
- *ControllerCoreRGRB15* (boolean)
- "1": RGR this bank
- "0": skip this bank
- true: RGR this bank
- false: skip this bank
- *ControllerCoreRGRtRASBInClkCycles* (unsigned int)
- Timing can be changed to explore optimum row granular refresh (ORGR)
- *ControllerCoreRGRtRRDB_LInClkCycles* (unsigned int)