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Merge branch '206-prepare-ci-testing' into 'master'

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Resolve "Prepare CI Testing"

See merge request ems/astdm/dram.sys!213
This commit is contained in:
Matthias Jung
2018-11-13 10:45:21 +01:00
parent fa21c71785 a69f204d8e
commit edb5e0b2aa
18 changed files with 587 additions and 1 deletions
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5
.gitlab-ci.yml
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@@ -1,7 +1,11 @@
image: gcc
variables:
GIT_STRATEGY: clone
stages:
- build
- WIDEIO
- DDR3
cache:
@@ -21,3 +25,4 @@ build:
include:
- '/DRAMSys/tests/DDR3/ci.yml'
- '/DRAMSys/tests/WIDEIO/ci.yml'

25
DRAMSys/tests/DDR3/ci.yml
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@@ -1,9 +1,11 @@
# Standard DDR3 Test:
example_ddr3:
stage: DDR3
script:
- cd build/simulator
- ./DRAMSys ../../DRAMSys/tests/DDR3/simulations/ddr3-example.xml ../../DRAMSys/tests/DDR3/
- ls
- ls -lah
- ls -lah ../../DRAMSys/tests/DDR3/expected/
- sqldiff ../../DRAMSys/tests/DDR3/expected/ddr3-example_ddr3_ch0.tdb ddr3-example_ddr3_ch0.tdb
- perl -e 'if(`sqldiff ../../DRAMSys/tests/DDR3/expected/ddr3-example_ddr3_ch0.tdb ddr3-example_ddr3_ch0.tdb` eq "") {exit(0)} else {exit(-1)}'
- cd ../traceAnalyzer
@@ -13,6 +15,27 @@ example_ddr3:
- build/simulator/ddr3-example_ddr3_ch0.tdb
expire_in: 2 days
# Testing Reordering with FR_FCFS Scheduling Algorithm:
fr_fcfs:
stage: DDR3
script:
- cd build/simulator
- ./DRAMSys ../../DRAMSys/tests/DDR3/simulations/ddr3-fr_fcfs.xml ../../DRAMSys/tests/DDR3/
- ls -lah
- ls -lah ../../DRAMSys/tests/DDR3/expected/
- sqldiff ../../DRAMSys/tests/DDR3/expected/ddr3-fr_fcfs_ddr3_ch0.tdb ddr3-fr_fcfs_ddr3_ch0.tdb
- perl -e 'if(`sqldiff ../../DRAMSys/tests/DDR3/expected/ddr3-fr_fcfs_ddr3_ch0.tdb ddr3-fr_fcfs_ddr3_ch0.tdb` eq "") {exit(0)} else {exit(-1)}'
- cd ../traceAnalyzer
- python3 ../../DRAMSys/traceAnalyzer/scripts/tests.py ../simulator/ddr3-fr_fcfs_ddr3_ch0.tdb | if ! grep "failed"; then exit 0; else exit 1; fi
allow_failure: true # TODO should be removed after first tests
artifacts:
paths:
- build/simulator/ddr3-fr_fcfs_ddr3_ch0.tdb
expire_in: 2 days
# Testing with TLM Protocol Cchecker
protocol_checker:
stage: DDR3
script:

50
DRAMSys/tests/DDR3/configs/mcconfigs/fr_fcfs.xml Normal file
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@@ -0,0 +1,50 @@
<mcconfig>
<OpenPagePolicy value="1" />
<MaxNrOfTransactions value="8" />
<Scheduler value="FR_FCFS" />
<Capsize value="5" />
<!-- 4 Modes: NoPowerDown, Staggered, TimeoutPDN, TimeoutSREF -->
<PowerDownMode value="NoPowerDown" />
<PowerDownTimeout value="100" />
<!-- Bankwise -->
<BankwiseLogic value="0"/>
<!-- Refresh yes, no -->
<ControllerCoreRefDisable value="0"/>
<!-- Refresh Mode. 1: 1X, 2: 2X, 4: 4X (e.g., DDR4) -->
<ControllerCoreRefMode value="1"/>
<!-- Number of AR commands in a tREFI in 1X mode -->
<ControllerCoreRefNumARCmdsIntREFI value="8192"/>
<!-- RGR -->
<ControllerCoreRGR value="0"/>
<ControllerCoreRGRRowInc value="1"/>
<!-- Banks to be refreshed in RGR mode. 1: yes, 0: no (max. 16 banks) -->
<ControllerCoreRGRB0 value="1"/>
<ControllerCoreRGRB1 value="1"/>
<ControllerCoreRGRB2 value="1"/>
<ControllerCoreRGRB3 value="1"/>
<ControllerCoreRGRB4 value="1"/>
<ControllerCoreRGRB5 value="1"/>
<ControllerCoreRGRB6 value="1"/>
<ControllerCoreRGRB7 value="1"/>
<ControllerCoreRGRB8 value="0"/>
<ControllerCoreRGRB9 value="0"/>
<ControllerCoreRGRB10 value="0"/>
<ControllerCoreRGRB11 value="0"/>
<ControllerCoreRGRB12 value="0"/>
<ControllerCoreRGRB13 value="0"/>
<ControllerCoreRGRB14 value="0"/>
<ControllerCoreRGRB15 value="0"/>
<!-- Timings for RGR normal or optimal values -->
<ControllerCoreRGRtRASBInClkCycles value="22"/>
<ControllerCoreRGRtRRDB_LInClkCycles value="2"/>
<ControllerCoreRGRtRRDB_SInClkCycles value="2"/>
<ControllerCoreRGRtRPBInClkCycles value="15"/>
<ControllerCoreRGRtRCBInClkCycles value="37"/>
<ControllerCoreRGRtFAWBInClkCycles value="0"/>
<!-- Postpone, pull-in -->
<ControllerCoreRefEnablePostpone value="0"/>
<ControllerCoreRefEnablePullIn value="0"/>
<ControllerCoreRefMaxPostponed value="8"/>
<ControllerCoreRefMaxPulledIn value="8"/>
<ControllerCoreRefForceMaxPostponeBurst value="0"/>
</mcconfig>

25
DRAMSys/tests/DDR3/simulations/ddr3-fr_fcfs.xml Normal file
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@@ -0,0 +1,25 @@
<simulation>
<!-- Simulation file identifier -->
<simulationid id="ddr3-fr_fcfs"></simulationid>
<!-- Configuration for the DRAMSys Simulator -->
<simconfig src="ddr3.xml" />
<!-- Temperature Simulator Configuration -->
<thermalconfig src="config.xml" />
<!-- Memory Device Specification: Which Device is on the DDR3 DIMM -->
<memspec src="MICRON_1Gb_DDR3-1600_8bit_G.xml"></memspec>
<!-- Addressmapping Configuration of the Memory Controller -->
<addressmapping src="am_ddr3_8x1Gbx8_dimm_p1KB_brc.xml"></addressmapping>
<!-- Memory Controller Configuration: -->
<mcconfig src="fr_fcfs.xml"/>
<!--
The following trace setup is only used in standalone mode.
In library mode e.g. in Platform Architect the trace setup is ignored.
-->
<tracesetup>
<!--
This device mimics an image processing application
running on an FPGA with 200 Mhz.
-->
<device clkMhz="200">ddr3_example.stl</device>
</tracesetup>
</simulation>

28
DRAMSys/tests/WIDEIO/ci.yml Normal file
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@@ -0,0 +1,28 @@
example_wideio:
stage: WIDEIO
script:
# Generate specific traces for WIDEIO:
- cd DRAMSys/tests/WIDEIO/traces/
- perl generator.pl
- cd ../../../../
# Run DRAMSys
- cd build/simulator
- ./DRAMSys ../../DRAMSys/tests/WIDEIO/simulations/wideio-example.xml ../../DRAMSys/tests/WIDEIO/
- ls
# Run Traceanalyzer testing scripts:
- cd ../traceAnalyzer
- python3 ../../DRAMSys/traceAnalyzer/scripts/tests.py ../simulator/wideio-example_wideio_ch0.tdb | if ! grep "failed"; then exit 0; else exit 1; fi
- python3 ../../DRAMSys/traceAnalyzer/scripts/tests.py ../simulator/wideio-example_wideio_ch1.tdb | if ! grep "failed"; then exit 0; else exit 1; fi
- python3 ../../DRAMSys/traceAnalyzer/scripts/tests.py ../simulator/wideio-example_wideio_ch2.tdb | if ! grep "failed"; then exit 0; else exit 1; fi
- python3 ../../DRAMSys/traceAnalyzer/scripts/tests.py ../simulator/wideio-example_wideio_ch3.tdb | if ! grep "failed"; then exit 0; else exit 1; fi
allow_failure: true # TODO: should be removed once the problems are fixed!
artifacts:
paths:
- build/simulator/wideio-example_wideio_ch0.tdb
- build/simulator/wideio-example_wideio_ch1.tdb
- build/simulator/wideio-example_wideio_ch2.tdb
- build/simulator/wideio-example_wideio_ch3.tdb
expire_in: 2 days

8
DRAMSys/tests/WIDEIO/configs/amconfigs/am_wideio_brc.xml Executable file
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@@ -0,0 +1,8 @@
<!-- Bank Row Column -->
<addressmapping>
<channel from="27" to="28" />
<bank from="24" to="26" />
<row from="11" to="23" />
<column from="4" to="10" />
<bytes from="0" to="3" />
</addressmapping>

8
DRAMSys/tests/WIDEIO/configs/amconfigs/am_wideio_rbc.xml Executable file
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@@ -0,0 +1,8 @@
<!-- Row Bank Column -->
<addressmapping>
<channel from="27" to="28" />
<row from="14" to="26" />
<bank from="11" to="13" />
<column from="4" to="10" />
<bytes from="0" to="3" />
</addressmapping>

50
DRAMSys/tests/WIDEIO/configs/mcconfigs/fifoStrict.xml Normal file
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@@ -0,0 +1,50 @@
<mcconfig>
<OpenPagePolicy value="1" />
<MaxNrOfTransactions value="8" />
<Scheduler value="FIFO_STRICT" />
<Capsize value="5" />
<!-- 4 Modes: NoPowerDown, Staggered, TimeoutPDN, TimeoutSREF -->
<PowerDownMode value="NoPowerDown" />
<PowerDownTimeout value="100" />
<!-- Bankwise -->
<BankwiseLogic value="0"/>
<!-- Refresh yes, no -->
<ControllerCoreRefDisable value="0"/>
<!-- Refresh Mode. 1: 1X, 2: 2X, 4: 4X (e.g., DDR4) -->
<ControllerCoreRefMode value="1"/>
<!-- Number of AR commands in a tREFI in 1X mode -->
<ControllerCoreRefNumARCmdsIntREFI value="8192"/>
<!-- RGR -->
<ControllerCoreRGR value="0"/>
<ControllerCoreRGRRowInc value="1"/>
<!-- Banks to be refreshed in RGR mode. 1: yes, 0: no (max. 16 banks) -->
<ControllerCoreRGRB0 value="1"/>
<ControllerCoreRGRB1 value="1"/>
<ControllerCoreRGRB2 value="1"/>
<ControllerCoreRGRB3 value="1"/>
<ControllerCoreRGRB4 value="1"/>
<ControllerCoreRGRB5 value="1"/>
<ControllerCoreRGRB6 value="1"/>
<ControllerCoreRGRB7 value="1"/>
<ControllerCoreRGRB8 value="0"/>
<ControllerCoreRGRB9 value="0"/>
<ControllerCoreRGRB10 value="0"/>
<ControllerCoreRGRB11 value="0"/>
<ControllerCoreRGRB12 value="0"/>
<ControllerCoreRGRB13 value="0"/>
<ControllerCoreRGRB14 value="0"/>
<ControllerCoreRGRB15 value="0"/>
<!-- Timings for RGR normal or optimal values -->
<ControllerCoreRGRtRASBInClkCycles value="22"/>
<ControllerCoreRGRtRRDB_LInClkCycles value="2"/>
<ControllerCoreRGRtRRDB_SInClkCycles value="2"/>
<ControllerCoreRGRtRPBInClkCycles value="15"/>
<ControllerCoreRGRtRCBInClkCycles value="37"/>
<ControllerCoreRGRtFAWBInClkCycles value="0"/>
<!-- Postpone, pull-in -->
<ControllerCoreRefEnablePostpone value="0"/>
<ControllerCoreRefEnablePullIn value="0"/>
<ControllerCoreRefMaxPostponed value="8"/>
<ControllerCoreRefMaxPulledIn value="8"/>
<ControllerCoreRefForceMaxPostponeBurst value="0"/>
</mcconfig>

61
DRAMSys/tests/WIDEIO/configs/memspecs/wideio.xml Normal file
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@@ -0,0 +1,61 @@
<!DOCTYPE memspec SYSTEM "memspec.dtd">
<memspec>
<parameter id="memoryId" type="string" value="Matze_WideIO" />
<parameter id="memoryType" type="string" value="WIDEIO_SDR" />
<memarchitecturespec>
<parameter id="width" type="uint" value="128" />
<parameter id="nbrOfBanks" type="uint" value="8" />
<parameter id="nbrOfColumns" type="uint" value="128" />
<parameter id="nbrOfRows" type="uint" value="8192" />
<parameter id="dataRate" type="uint" value="1" />
<parameter id="burstLength" type="uint" value="4" />
</memarchitecturespec>
<memtimingspec>
<parameter id="clkMhz" type="double" value="166" />
<parameter id="RC" type="uint" value="9" /><!--tRP+tRAS-->
<parameter id="RCD" type="uint" value="3" />
<parameter id="RL" type="uint" value="3" />
<parameter id="RP" type="uint" value="3" />
<parameter id="RFC" type="uint" value="22" />
<parameter id="RAS" type="uint" value="6" />
<parameter id="WL" type="uint" value="1" />
<parameter id="AL" type="uint" value="0" />
<parameter id="RTP" type="uint" value="4" />
<parameter id="WR" type="uint" value="2" />
<parameter id="XP" type="uint" value="2" />
<parameter id="XS" type="uint" value="20" /><!--tRFC+2clk-->
<parameter id="REFI" type="uint" value="1300" />
<parameter id="TAW" type="uint" value="10" />
<parameter id="RRD" type="uint" value="2" />
<parameter id="CCD" type="uint" value="1" />
<parameter id="WTR" type="uint" value="3" />
<parameter id="CKE" type="uint" value="3" />
<parameter id="CKESR" type="uint" value="3" />
</memtimingspec>
<mempowerspec>
<parameter id="idd0" type="double" value="5.88" />
<parameter id="idd02" type="double" value="21.18" />
<parameter id="idd2p0" type="double" value="0.05" />
<parameter id="idd2p02" type="double" value="0.17" />
<parameter id="idd2p1" type="double" value="0.05" />
<parameter id="idd2p12" type="double" value="0.17" />
<parameter id="idd2n" type="double" value="0.13" />
<parameter id="idd2n2" type="double" value="4.04" />
<parameter id="idd3p0" type="double" value="0.25" />
<parameter id="idd3p02" type="double" value="1.49" />
<parameter id="idd3p1" type="double" value="0.25" />
<parameter id="idd3p12" type="double" value="1.49" />
<parameter id="idd3n" type="double" value="0.52" />
<parameter id="idd3n2" type="double" value="6.55" />
<parameter id="idd4r" type="double" value="1.41" />
<parameter id="idd4r2" type="double" value="85.73" />
<parameter id="idd4w" type="double" value="1.42" />
<parameter id="idd4w2" type="double" value="60.79" />
<parameter id="idd5" type="double" value="14.43" />
<parameter id="idd52" type="double" value="48.17" />
<parameter id="idd6" type="double" value="0.07" />
<parameter id="idd62" type="double" value="0.27" />
<parameter id="vdd" type="double" value="1.8" />
<parameter id="vdd2" type="double" value="1.2" />
</mempowerspec>
</memspec>

24
DRAMSys/tests/WIDEIO/configs/simulator/wideio.xml Normal file
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@@ -0,0 +1,24 @@
<simconfig>
<SimulationName value="wideio" />
<Debug value="0" />
<DatabaseRecording value="1" />
<PowerAnalysis value="1" />
<EnableWindowing value = "1" />
<WindowSize value="1000" />
<ThermalSimulation value="0"/>
<SimulationProgressBar value="1"/>
<NumberOfMemChannels value="4"/>
<NumberOfDevicesOnDIMM value = "1" />
<CheckTLM2Protocol value = "0" />
<ECCControllerMode value = "Disabled" />
<ErrorChipSeed value="42" />
<ErrorCSVFile value="../../DRAMSys/library/resources/error/wideio.csv" />
<!-- Modes:
- NoStorage,
- Store (store data without errormodel),
- ErrorModel (store data with errormodel)
-->
<StoreMode value="NoStorage" />
<UseMalloc value="0" />
</simconfig>

14
DRAMSys/tests/WIDEIO/configs/thermalsim/config.xml Normal file
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@@ -0,0 +1,14 @@
<!-- Temperature Simulator Configuration (used for all simulation setups) -->
<thermalsimconfig>
<TemperatureScale value="Celsius" />
<StaticTemperatureDefaultValue value="89" />
<ThermalSimPeriod value="100" />
<ThermalSimUnit value="us" />
<PowerInfoFile value="powerInfo.xml"/>
<IceServerIp value="127.0.0.1" />
<IceServerPort value="11880" />
<SimPeriodAdjustFactor value="10" />
<NPowStableCyclesToIncreasePeriod value="5" />
<GenerateTemperatureMap value="1" />
<GeneratePowerMap value="1" />
</thermalsimconfig>

45
DRAMSys/tests/WIDEIO/configs/thermalsim/core.flp Executable file
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@@ -0,0 +1,45 @@
CPUs :
position 0, 0 ;
dimension 2750, 4300 ;
GPU :
position 3350, 0 ;
dimension 2750, 4000 ;
BASEBAND1 :
position 4250, 4000 ;
dimension 1850, 3300 ;
BASEBAND2 :
position 3350, 7300 ;
dimension 2750, 3300 ;
LLCACHE :
position 0, 4300 ;
dimension 1900, 3000 ;
DRAMCTRL1 :
position 1900, 4300 ;
dimension 850, 3000 ;
DRAMCTRL2 :
position 3350, 4000 ;
dimension 900, 3300 ;
TSVS :
position 2750, 2300 ;
dimension 600, 6000 ;
ACELLERATORS :
position 0, 7300 ;
dimension 2750, 3300 ;

16
DRAMSys/tests/WIDEIO/configs/thermalsim/mem.flp Executable file
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@@ -0,0 +1,16 @@
channel0 :
position 150, 100 ;
dimension 2600, 5200 ;
channel1 :
position 3350, 100 ;
dimension 2600, 5200 ;
channel2 :
position 150, 5300 ;
dimension 2600, 5200 ;
channel3 :
position 3350, 5300 ;
dimension 2600, 5200 ;

8
DRAMSys/tests/WIDEIO/configs/thermalsim/powerInfo.xml Normal file
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@@ -0,0 +1,8 @@
<powerInfo>
<!-- Power information must be provided for all floor plan elements -->
<dram_die_channel0 init_pow="0" threshold="1.0" />
<dram_die_channel1 init_pow="0" threshold="1.0" />
<dram_die_channel2 init_pow="0" threshold="1.0" />
<dram_die_channel3 init_pow="0" threshold="1.0" />
</powerInfo>

49
DRAMSys/tests/WIDEIO/configs/thermalsim/stack.stk Executable file
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@@ -0,0 +1,49 @@
material SILICON :
thermal conductivity 1.30e-4 ;
volumetric heat capacity 1.628e-12 ;
material BEOL :
thermal conductivity 2.25e-6 ;
volumetric heat capacity 2.175e-12 ;
material COPPER :
thermal conductivity 4.01e-04 ;
volumetric heat capacity 3.37e-12 ;
top heat sink :
//sink height 1e03, area 100e06, material COPPER ;
//spreader height 0.5e03, area 70e06, material SILICON ;
heat transfer coefficient 1.3e-09 ;
temperature 318.15 ;
dimensions :
chip length 6100, width 10600 ;
cell length 100, width 100 ;
layer PCB :
height 10 ;
material BEOL ;
die DRAM :
layer 58.5 SILICON ;
source 2 SILICON ;
layer 1.5 BEOL ;
layer 58.5 SILICON ;
stack:
die DRAM_DIE DRAM floorplan "./mem.flp" ;
layer CONN_TO_PCB PCB ;
solver:
transient step 0.01, slot 0.05 ;
initial temperature 300.0 ;
output:
Tflpel(DRAM_DIE.channel0 , "temp_flp_element_ch0.txt" , average , slot );
Tflpel(DRAM_DIE.channel1 , "temp_flp_element_ch1.txt" , average , slot );
Tflpel(DRAM_DIE.channel2 , "temp_flp_element_ch2.txt" , average , slot );
Tflpel(DRAM_DIE.channel3 , "temp_flp_element_ch3.txt" , average , slot );
Tmap (DRAM_DIE, "output1.txt", slot) ;
Pmap (DRAM_DIE, "output2.txt", slot) ;

73
DRAMSys/tests/WIDEIO/scripts/createTraceDB.sql Normal file
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@@ -0,0 +1,73 @@
DROP TABLE IF EXISTS Phases;
DROP TABLE IF EXISTS GeneralInfo;
DROP TABLE IF EXISTS Comments;
DROP TABLE IF EXISTS ranges;
DROP TABLE IF EXISTS Transactions;
DROP TABLE IF EXISTS DebugMessages;
DROP TABLE IF EXISTS Power;
CREATE TABLE Phases(
ID INTEGER PRIMARY KEY,
PhaseName TEXT,
PhaseBegin INTEGER,
PhaseEnd INTEGER,
Transact INTEGER
);
CREATE TABLE GeneralInfo(
NumberOfTransactions INTEGER,
TraceEnd INTEGER,
NumberOfBanks INTEGER,
clk INTEGER,
UnitOfTime TEXT,
MCconfig TEXT,
Memspec TEXT,
Traces TEXT,
WindowSize INTEGER,
FlexibleRefresh INTEGER,
MaxRefBurst INTEGER,
ControllerThread INTEGER
);
CREATE TABLE Power(
time DOUBLE,
AveragePower DOUBLE
);
CREATE TABLE Comments(
Time INTEGER,
Text TEXT
);
CREATE TABLE DebugMessages(
Time INTEGER,
Message TEXT
);
-- use SQLITE R* TREE Module to make queries on timespans effecient (see http://www.sqlite.org/rtree.html)
CREATE VIRTUAL TABLE ranges USING rtree(
id,
begin, end
);
CREATE TABLE Transactions(
ID INTEGER,
Range INTEGER,
Address INTEGER,
Burstlength INTEGER,
TThread INTEGER,
TChannel INTEGER,
TBank INTEGER,
TBankgroup INTEGER,
TRow INTEGER,
TColumn INTEGER,
DataStrobeBegin INTEGER,
DataStrobeEnd INTEGER,
TimeOfGeneration INTEGER,
Command TEXT
);
CREATE INDEX ranges_index ON Transactions(Range);
CREATE INDEX "phasesTransactions" ON "Phases" ("Transact" ASC);
CREATE INDEX "messageTimes" ON "DebugMessages" ("Time" ASC);

24
DRAMSys/tests/WIDEIO/simulations/wideio-example.xml Normal file
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@@ -0,0 +1,24 @@
<simulation>
<!-- Simulation file identifier -->
<simulationid id="wideio-example"></simulationid>
<!-- Configuration for the DRAMSys Simulator -->
<simconfig src="wideio.xml" />
<!-- Temperature Simulator Configuration -->
<thermalconfig src="config.xml" />
<!-- Memory Device Specification: Which Device is used for Wide I/O -->
<memspec src="wideio.xml"></memspec>
<!-- Addressmapping Configuration of the Memory Controller -->
<addressmapping src="am_wideio_brc.xml"></addressmapping>
<!-- Memory Controller Configuration -->
<mcconfig src="fifoStrict.xml"/>
<!--
The following trace setup is only used in standalone mode.
In library mode e.g. in Platform Architect the trace setup is ignored.
-->
<tracesetup>
<!--
This device mimics an processor running at 1 GHz.
-->
<device clkMhz="1000">wideio.stl</device>
</tracesetup>
</simulation>

75
DRAMSys/tests/WIDEIO/traces/generator.pl Normal file
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@@ -0,0 +1,75 @@
#!/usr/bin/perl -w
use warnings;
use strict;
# Width: 128 bit
#
# Mapping:
# 28 | 27 26 25 24 | 23 22 21 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 | 7 6 5 4 | 3 2 1 0
# H | H B B B | R R R R | R R R R | R R R R | R C C C | C C C C | Y Y Y Y
open(OUT, "> wideio.stl");
my $length = 100000;
my $size = 0x10;
my $channelOffset = 0x8000000;
my $state = 0;
# state 0: reads only linear
# state 1: reads only random
# state 2: read and writes linear
for(my $i=0; $i < $length; $i += 4)
{
my $r = 0;
if($state == 0)
{
print OUT ($i+0).": read ".sprintf("0x%x",($size*$i)+0*$channelOffset)."\n";
print OUT ($i+1).": read ".sprintf("0x%x",($size*$i)+1*$channelOffset)."\n";
print OUT ($i+2).": read ".sprintf("0x%x",($size*$i)+2*$channelOffset)."\n";
print OUT ($i+3).": read ".sprintf("0x%x",($size*$i)+3*$channelOffset)."\n";
}
elsif($state == 1)
{
$r = int(rand($channelOffset));
print OUT ($i+0).": read ".sprintf("0x%x",($size*$r)+0*$channelOffset)."\n";
$r = int(rand($channelOffset));
print OUT ($i+1).": read ".sprintf("0x%x",($size*$r)+1*$channelOffset)."\n";
$r = int(rand($channelOffset));
print OUT ($i+2).": read ".sprintf("0x%x",($size*$r)+2*$channelOffset)."\n";
$r = int(rand($channelOffset));
print OUT ($i+3).": read ".sprintf("0x%x",($size*$r)+3*$channelOffset)."\n";
}
elsif($state == 2)
{
my $rw = int(rand(2))%2;
if($rw == 0)
{
print OUT "$i: read ".sprintf("0x%x",($size*$i)+0*$channelOffset)."\n";
print OUT "$i: read ".sprintf("0x%x",($size*$i)+1*$channelOffset)."\n";
print OUT "$i: read ".sprintf("0x%x",($size*$i)+2*$channelOffset)."\n";
print OUT "$i: read ".sprintf("0x%x",($size*$i)+3*$channelOffset)."\n";
}
else
{
print OUT "$i: write ".sprintf("0x%x",($size*$i)+0*$channelOffset)."\n";
print OUT "$i: write ".sprintf("0x%x",($size*$i)+1*$channelOffset)."\n";
print OUT "$i: write ".sprintf("0x%x",($size*$i)+2*$channelOffset)."\n";
print OUT "$i: write ".sprintf("0x%x",($size*$i)+3*$channelOffset)."\n";
}
}
else
{
print "Error generating traces (".$state.")";
exit(-1);
}
if(($i != 0) && (($i % 1000) == 0))
{
# GOTO next state every 1000st request:
$state = ($state + 1) % 3;
}
}
close(OUT);